Process for manufacturing a MOS-technology power device chip and package assembly
First Claim
1. A method for making a MOS-technology power device chip and package assembly comprising the steps of:
- a) forming a plurality of elementary functional units in a semiconductor material layer, wherein each elementary unit includesa first doped region of a first conductivity type in said semiconductor layer, anda second doped region of a second conductivity type inside said first doped region;
b) forming sub-pluralities of elementary functional units in said plurality of elementary functional units;
c) contacting each second doped region of each sub-plurality by a same metal plate so that each metal plate corresponding to each sub-plurality is electrically insulated from one another;
d) connecting each metal plate, through a bonding wire, to a source electrode pin of said package;
e) separating said sub-pluralities of elementary functional units by regions of said semiconductor material layer where no elementary functional units are formed;
f) covering said semiconductor material layer by a conductive insulated gate layer partially extending over each first doped region;
g) contacting said insulated gate layer by gate metal mesh surrounding each metal plate;
h) connecting said gate metal mesh to at least one gate metal pad;
i) connecting said gate metal pad, by means of a bonding wire, to a pin of said package; and
j) soldering a bottom surface of said chip onto a metal plate of said package.
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Abstract
A process for manufacturing a MOS-technology power device chip and package assembly, the MOS-technology power device chip comprises a semiconductor material layer in which a plurality of elementary functional units is integrated, each elementary functional unit contributing a respective fraction to an overall current and including a first doped region of a first conductivity type formed in the semiconductor layer, and a second doped region of a second conductivity type formed inside the first doped region; the package comprises a plurality of pins for the external electrical and mechanical connection; the plurality of elementary functional its is composed of sub-pluralities of elementary functional units, the second doped regions of all the elementary functional units of each sub-plurality being contacted by a same respective metal plate electrically insulated from the metal plates contacting the second doped regions of all the elementary functional units of the other sub-pluralities; each of the metal plates are connected, through a respective bonding wire, to a respective pin of the package.
38 Citations
23 Claims
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1. A method for making a MOS-technology power device chip and package assembly comprising the steps of:
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a) forming a plurality of elementary functional units in a semiconductor material layer, wherein each elementary unit includes a first doped region of a first conductivity type in said semiconductor layer, and a second doped region of a second conductivity type inside said first doped region; b) forming sub-pluralities of elementary functional units in said plurality of elementary functional units; c) contacting each second doped region of each sub-plurality by a same metal plate so that each metal plate corresponding to each sub-plurality is electrically insulated from one another; d) connecting each metal plate, through a bonding wire, to a source electrode pin of said package; e) separating said sub-pluralities of elementary functional units by regions of said semiconductor material layer where no elementary functional units are formed; f) covering said semiconductor material layer by a conductive insulated gate layer partially extending over each first doped region; g) contacting said insulated gate layer by gate metal mesh surrounding each metal plate; h) connecting said gate metal mesh to at least one gate metal pad; i) connecting said gate metal pad, by means of a bonding wire, to a pin of said package; and j) soldering a bottom surface of said chip onto a metal plate of said package. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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12. A method for making a MOS-technology power device chip and package assembly as claimed in claim l, wherein each said source electrode pin is electrically isolated from one another.
Specification