Method of vertically integrating microelectronic systems

• US 5,851,894 A
• Filed: 05/03/1996
• Issued: 12/22/1998
• Est. Priority Date: 05/05/1995
• Status: Expired due to Term

• Current Assignee: Fraunhofer Gesellschaft Zur Foerderung Der Angewandten Forsching E.V.
• Original Assignee: Fraunhofer Gesellschaft Zur Foerderung Der Angewandten Forsching E.V.
• Inventors: Ramm, Peter
• Primary Examiner(s): GRAYBILL, DAVID E
• Application Number:
  US08/642,047
• Time in Patent Office: 963 Days
• Field of Search: 438/311, 438/459, 438/690, 438/691, 438/692, 438/693, 438/759, 438/940, 438/975, 438/977, 438/385, 438/435, 438/485, 438/495
• US Class Current: 438/311
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 438/94 Laser ablative material removal
• CPC Class Codes: Y10S 438/975 Substrate or mask aligning feature
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A method of fabricating vertically integrated microelectronic systems by CMOS-compatible standard semiconductor process technology, by independently processing individual component layers of at least two separate substrates, including the formation of via holes penetrating through all existing component layers and connecting together the front surfaces of the two substrates, thinning the reverse surface of one of the substrates down to the via holes, increasing the depth of the via holes to a metallization plane of the other substrate and forming electrically conductive connections between the two substrates through the via holes.

Claims

1. A method of vertically integrating microelectronic systems, comprising the steps of:

providing a first substrate comprising a first side which in an area of a first major surface comprises at least one first layer containing circuit structures and at least one first metallized metallization level;

opening in the area of said first major surface a plurality of via holes of a depth sufficient for penetrating said at least one first circuit structure containing layer;

providing a second substrate comprising a side which in an area of a second major surface comprises at least one second layer containing circuit structures and at least one second metallized metallization level;

connecting said first substrate to said second substrate by putting together said side of said first major surface and said side of said second major surface in aligned relationship, thereby to provide a stack of substrates;

thinning the stack of substrates at a side of said first substrate opposite said first side for opening said via holes therein;

increasing said depth of said via holes down to the metallization of said metallization level of said second substrate; and

providing means extending through said via holes for forming an electrically conductive connection between said metallization of said first and said metallization of said second metallization level.

2. The method of claim 1, wherein said opening of said via holes includes the penetration thereof through said metallization in said first substrate.

3. The method of claim 1, wherein said first and second substrates are connected in an aligned manner by alignment indicia provided in said area of said first major surface of said first substrate and said area of said second major surface of said second substrate.

4. The method of claim 1, wherein said via holes are opened by an etching process.

5. The method of claim 4, wherein said etching process includes anisotropic etching through said at least one first layer containing circuit structures and subsequent trench etching to substantially 10 μ

m below said at least one first layer.

6. The method of claim 5, wherein a buried oxide layer is provided as an etching stop.

7. The method of claim 1, wherein said thinning is performed by etching.

8. The method of claim 6, wherein said thinning is performed by grinding.

9. The method of claim 1, wherein said first substrate comprises an SOI substrate and wherein thinning is performed down to an oxide layer buried in said SOI substrate followed by removal of said oxide layer with the substrate material acting as an etching stop.

10. The method of claim 1, wherein said first and second substrates are connected to each other by a bonding layer applied to said second major surface of said second substrate.

11. The method of claim 10, wherein said bonding layer is a passivation layer.

12. The method of claim 10, wherein said bonding layer provides a planarizing layer.

13. The method of claim 1, wherein said step of connecting said first and second substrates comprises treatment of at least one of said first and second major surfaces to provide a direct bond with the other of said first and second major surfaces.

14. The method of claim 1, wherein said connecting step is preceded by forming a substantially planar express surface.

15. The method of claim 1, wherein said connecting step is preceded by forming a planarized layer.

16. The method of claim 1, wherein the step of increasing the depth of said via holes is performed by anisotropic etching and wherein the material of said first substrate is utilized as a etching mask.

17. The method of claim 1, wherein said step of providing said means for forming said electrically conductive connection comprises the following steps:

precipitating within said via holes a bonding and barrier layer;

precipitating in said via holes a metallic substance;

chemomechanically grinding off from said surface of said stack of substrates said bonding and barrier layer and said metallic substance.

18. The method of claim 10, wherein said first and second substrates are connected by the step of applying a layer of polyimide to said second substrate.

19. The method of claim 1, wherein said step of providing means for forming an electrically conductive connection comprises precipitating a metal to cover the via holes from the top surface of the first substrate to the metallization of the bottom substrate.

20. The method of claim 19, wherein said metal is initially precipitated as a layer of titanium nitride followed by a tungsten metallization of predetermined shape.