Method of forming a dram cell with a crown-fin-pillar structure capacitor

• US 5,851,897 A
• Filed: 11/18/1996
• Issued: 12/22/1998
• Est. Priority Date: 11/18/1996
• Status: Expired due to Term

• Current Assignee: Powerchip Semiconductor Corporation (Powerchip Technology Corporation)
• Original Assignee: Powerchip Semiconductor Corporation (Powerchip Technology Corporation)
• Inventors: Wu, Shye Lin
• Primary Examiner(s): Brown, Peter Toby
• Assistant Examiner(s): Thomas, Toniae M.
• Application Number:
  US08/752,194
• Time in Patent Office: 764 Days
• Field of Search: 438/253, 438/254, 438/396, 438/397, 438/212, 438/220, 438/430, 257/307, 257/308, 148/DIG. 14
• US Class Current: 438/397
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/318 the storage electrode having multiple segments

Abstract

The present invention is a method of manufacturing a high density capacitors for use in semiconductor memories. High etching selectivity between BPSG (borophososilicate glass) and CVD-oxide (chemical vapor deposition oxide) is used to fabricate a crown shape capacitor with a plurality of horizontal fins. First, a first polysilicon layer is formed on a semiconductor substrate. A composition layer consists of BPSG and silicon oxide formed on a the first polysilicon layer. Then a contact hole is formed in the composition layer and the first polysilicon layer. A highly selective etching is then used to etch the BPSG sublayers of the composition layer. Next, a second polysilicon layer is formed in the contact hole and the composition layer. Then photolithgraphy and etching process is used to etch the second polysilicon layer, composition layer and first polysilicon layer. A third polysilicon layer is subsequently formed on the second polysilicon layer. An anisotropic etching is performed to etching the second and the third polysilicon layer. Then the composition layer is removed by BOE solution. A dielectric film is then formed along the surface of the first, second and third polysilicon layer. Finally, a forth polysilicon layer is formed on the dielectric film. Thus, a capacitor with a plurality of horizontal fins is formed.

Claims

1. A method for manufacturing an integrated circuit capacitor, the method comprising the steps of:

forming a first conductive layer over a semiconductor substrate;

forming a composition layer with a plurality of sublayers on said first conductive layer, said composition layer including a plurality of sublayers, at least two of said sublayers having a susceptibility to etching that differs;

forming a contact hole in said composition layer and said first conductive layer to said substrate;

selectively etching said composition layer through said contact hole to etch one of said at least two of said sublayers;

forming a second conductive layer on said composition layer, in said contact hole;

patterning a photoresist on said second conductive layer;

etching said second conductive layer, said composition layer and said first conductive layer using said photoresist as an etching mask;

removing said photoresist;

then

forming a third conductive layer on said second conductive layer, said composition layer, and said first conductive layer;

etching said second conductive layer, said third conductive layer to expose a top sublayer of said composition layer;

removing said composition layer;

forming a dielectric film on the surface of said first conductive layer, second conductive layer and said third conductive layer; and

forming a forth conductive layer over said dielectric film.

2. The method of claim 1, further comprises following steps before forming said first conductive layer:

forming a dielectric layer on said substrate; and

forming a nitride layer on said dielectric layer.

3. The method of claim 1, further comprises a step of removing said nitride layer before forming said dielectric film.

4. The method of claim 1, wherein said sublayers are further grouped into odd sublayers and even sublayers, and said odd sublayers are BPSG and said even sublayers are silicon dioxide.

5. The method of claim 1 wherein said sublayers are further grouped into odd sublayers and even sublayers, and said odd sublayers are BPSG and said even sublayers are BSG.

6. The method of claim 1, wherein said sublayers are further grouped into odd sublayers and even sublayers, and said even sublayers are BPSG and said odd sublayers are silicon dioxide.

7. The method of claim 1 wherein said sublayers are further grouped into odd sublayers and even sublayers, and said even sublayers are BPSG and said odd sublayers are BSG.

8. The method of claim 1, wherein said first conductive layer has a thickness about 300-3000 angstroms.

9. The method of claim 2, wherein said dielectric layer is formed of silicon oxide.

10. The method of claim 9, wherein said dielectric layer has a thickness about 3000-10000 angstroms.

11. The method of claim 4, wherein said BPSG sublayers have a thickness of a range between 300-1000 angstroms, said silicon dioxide layers have a thickness of a range between 300-1000 angstroms.

12. The method of claim 11, wherein the step of etching the composition layer is done with a low pressure HF vapor.

13. The method of claim 5, wherein said BPSG sublayers have a thickness of a range between 300-1000 angstroms, said BSG layers have a thickness of a range between 300-1000 angstroms.

14. The method of claim 13, wherein the step of etching the composition layer is done with a low pressure HF vapor.

15. The method of claim 6, wherein said BPSG sublayers have a thickness of a range between 300-1000 angstroms, said silicon dioxide layers have a thickness of a range between 300-1000 angstroms.

16. The method of claim 15, wherein the step of etching the composition layer is done with a low pressure HF vapor.

17. The method of claim 7, wherein said BPSG sublayers have a thickness of a range between 300-1000 angstroms, said silicon dioxide layers have a thickness of a range between 300-1000 angstroms.

18. The method of claim 17, wherein the step of etching the composition layer is done with a low pressure HF vapor.

19. The method of claim 1, wherein said second conductive layer is also formed between said plurality of sublayers.

20. The method of claim 1, wherein said second conductive layer has a thickness of a range between 300-3000 angstroms.

21. The method of claim 1, wherein the step of removing said composition layer is done using a BOE (buffer oxide etching) solution.

22. The method of claim 1, wherein said third conductive layer has a thickness of a range between 300-3000 angstroms.

23. The method of claim 1, wherein said forth conductive layer has a thickness of a range between 500-3000 angstroms.

24. The method of claim 1, wherein said dielectric film is formed of tantalum oxide(Ta₂ O₅).

25. The method of claim 1, wherein said dielectric film is formed of a triple film of oxide/nitride/oxide.

26. The method of claim 1, wherein said dielectric film is formed of a double film of nitride/oxide film.

27. The method of claim 1, wherein said dielectric film is formed of BST.

28. The method of claim 1, wherein said dielectric film is formed of PZT or PLZT.

29. The method of claim 1, wherein said first conductive layer, said second conductive layer, said third conductive layer and forth conductive layer are selected from the group of doped polysilicon, in-situ doped polysilicon, aluminum, copper, tungsten, and titanium combinations thereon.

30. A method for manufacturing an integrated circuit capacitor, the method comprising the steps of:

forming a first conductive layer over a semiconductor substrate;

forming a composition layer that consists of alternating sublayers of BPSG sublayers and silicon dioxide sublayers on said first conductive layer;

forming a contact hole in said composition layer and said first conductive layer;

etching said composition layer through said contact hole using highly selective etching to etch said BPSG layers;

forming a second conductive layer in said contact hole and over said composition layer;

patterning a photoresist on said second conductive layer;

etching said second conductive layer, composition layer and first conductive layer using said photoresist as an etching mask;

stripping said photoresist;

then

forming a third conductive layer on said second conductive layer, said composition layer, and said first conductive layer;

etching said third conductive layer and said second conductive layer to expose a top of said composition layer;

removing said composition layer;

forming a dielectric film on the surface of said first conductive layer, third conductive layer and said second conductive layer; and

forming a forth conductive layer over said dielectric film.

31. The method of claim 30, wherein the step of etching the composition layer is done with a low pressure HF vapor.

32. The method of claim 30, wherein the step of removing said composition layer is done using a BOE (buffer oxide etching) solution.

33. The method of claim 30, wherein said BPSG sublayers have a thickness of a range between 300-1000 angstroms, said silicon dioxide layers have a thickness of a range between 300-1000 angstroms.

34. A method of forming a crown shape polysilicon with a plurality of fins comprising the steps of:

forming a first polysilicon layer on a substrate;

forming a composition layer that consists of alternating BPSG layers and silicon dioxide layers on said first polysilicon layer;

forming a hole through said composition layer and said first polysilicon layer to said substrate;

using high selective etching to selectively etch said BPSG layers through said contact hole;

forming a second polysilicon layer on said substrate, in said hole and over said composition layer;

patterning a photoresist on said second polysilicon ayer;

etching said second polysilicon layer, said composition layer and said first polysilicon layer using said photoresist as an etching mask;

removing said photoresist;

then

forming a third polysilicon layer on said second polysilicon layer, said composition layer, and said first polysilicon layer;

etching said third polysilicon layer, second polysilicon layer to expose a top layer of said composition layer; and

removing said composition layer.

35. The method of claim 34, wherein the step of etching the composition layer is done with a low pressure HF vapor.

36. The method of claim 34, wherein the step of removing said composition layer is done using a BOE (buffer oxide etching) solution.