Method of forming a dram cell with a crown-fin-pillar structure capacitor
First Claim
1. A method for manufacturing an integrated circuit capacitor, the method comprising the steps of:
- forming a first conductive layer over a semiconductor substrate;
forming a composition layer with a plurality of sublayers on said first conductive layer, said composition layer including a plurality of sublayers, at least two of said sublayers having a susceptibility to etching that differs;
forming a contact hole in said composition layer and said first conductive layer to said substrate;
selectively etching said composition layer through said contact hole to etch one of said at least two of said sublayers;
forming a second conductive layer on said composition layer, in said contact hole;
patterning a photoresist on said second conductive layer;
etching said second conductive layer, said composition layer and said first conductive layer using said photoresist as an etching mask;
removing said photoresist;
thenforming a third conductive layer on said second conductive layer, said composition layer, and said first conductive layer;
etching said second conductive layer, said third conductive layer to expose a top sublayer of said composition layer;
removing said composition layer;
forming a dielectric film on the surface of said first conductive layer, second conductive layer and said third conductive layer; and
forming a forth conductive layer over said dielectric film.
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Accused Products
Abstract
The present invention is a method of manufacturing a high density capacitors for use in semiconductor memories. High etching selectivity between BPSG (borophososilicate glass) and CVD-oxide (chemical vapor deposition oxide) is used to fabricate a crown shape capacitor with a plurality of horizontal fins. First, a first polysilicon layer is formed on a semiconductor substrate. A composition layer consists of BPSG and silicon oxide formed on a the first polysilicon layer. Then a contact hole is formed in the composition layer and the first polysilicon layer. A highly selective etching is then used to etch the BPSG sublayers of the composition layer. Next, a second polysilicon layer is formed in the contact hole and the composition layer. Then photolithgraphy and etching process is used to etch the second polysilicon layer, composition layer and first polysilicon layer. A third polysilicon layer is subsequently formed on the second polysilicon layer. An anisotropic etching is performed to etching the second and the third polysilicon layer. Then the composition layer is removed by BOE solution. A dielectric film is then formed along the surface of the first, second and third polysilicon layer. Finally, a forth polysilicon layer is formed on the dielectric film. Thus, a capacitor with a plurality of horizontal fins is formed.
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Citations
36 Claims
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1. A method for manufacturing an integrated circuit capacitor, the method comprising the steps of:
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forming a first conductive layer over a semiconductor substrate; forming a composition layer with a plurality of sublayers on said first conductive layer, said composition layer including a plurality of sublayers, at least two of said sublayers having a susceptibility to etching that differs; forming a contact hole in said composition layer and said first conductive layer to said substrate; selectively etching said composition layer through said contact hole to etch one of said at least two of said sublayers; forming a second conductive layer on said composition layer, in said contact hole; patterning a photoresist on said second conductive layer; etching said second conductive layer, said composition layer and said first conductive layer using said photoresist as an etching mask; removing said photoresist;
thenforming a third conductive layer on said second conductive layer, said composition layer, and said first conductive layer; etching said second conductive layer, said third conductive layer to expose a top sublayer of said composition layer; removing said composition layer; forming a dielectric film on the surface of said first conductive layer, second conductive layer and said third conductive layer; and forming a forth conductive layer over said dielectric film. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29)
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30. A method for manufacturing an integrated circuit capacitor, the method comprising the steps of:
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forming a first conductive layer over a semiconductor substrate; forming a composition layer that consists of alternating sublayers of BPSG sublayers and silicon dioxide sublayers on said first conductive layer; forming a contact hole in said composition layer and said first conductive layer; etching said composition layer through said contact hole using highly selective etching to etch said BPSG layers; forming a second conductive layer in said contact hole and over said composition layer; patterning a photoresist on said second conductive layer; etching said second conductive layer, composition layer and first conductive layer using said photoresist as an etching mask; stripping said photoresist;
thenforming a third conductive layer on said second conductive layer, said composition layer, and said first conductive layer; etching said third conductive layer and said second conductive layer to expose a top of said composition layer; removing said composition layer; forming a dielectric film on the surface of said first conductive layer, third conductive layer and said second conductive layer; and forming a forth conductive layer over said dielectric film. - View Dependent Claims (31, 32, 33)
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34. A method of forming a crown shape polysilicon with a plurality of fins comprising the steps of:
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forming a first polysilicon layer on a substrate; forming a composition layer that consists of alternating BPSG layers and silicon dioxide layers on said first polysilicon layer; forming a hole through said composition layer and said first polysilicon layer to said substrate; using high selective etching to selectively etch said BPSG layers through said contact hole; forming a second polysilicon layer on said substrate, in said hole and over said composition layer; patterning a photoresist on said second polysilicon ayer; etching said second polysilicon layer, said composition layer and said first polysilicon layer using said photoresist as an etching mask; removing said photoresist;
thenforming a third polysilicon layer on said second polysilicon layer, said composition layer, and said first polysilicon layer; etching said third polysilicon layer, second polysilicon layer to expose a top layer of said composition layer; and removing said composition layer. - View Dependent Claims (35, 36)
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Specification