Power inverter having three or more parallel driven PWM-type power inverting units

• US 5,852,554 A
• Filed: 06/12/1997
• Issued: 12/22/1998
• Est. Priority Date: 06/12/1996
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Meidensha (Meidensha Corporation)
• Original Assignee: Kabushiki Kaisha Meidensha (Meidensha Corporation)
• Inventors: Yamamoto, Yasuhiro
• Primary Examiner(s): NGUYEN, MATTHEW VAN
• Application Number:
  US08/873,923
• Time in Patent Office: 558 Days
• Field of Search: 363/34, 363/36, 363/37, 363/65, 363/71, 363/95, 363/97, 363/131
• US Class Current: 363/71
• CPC Class Codes: H02M 7/493 the static converters being arranged for operation in parallel

Abstract

A power inverter having: three or more PWM-type power inverting units which are so arranged and constructed as to be enabled to be driven in parallel; a plurality of integrated interphase reactors, each of which is so arranged and constructed as to synthesize each of the same phase output currents of the respective PWM-type inverting units and supply the synthesized phase output current to a load such as a three-phase induction motor; a plurality of current balance controllers, each of which is so arranged and constructed as to carry out a retardation correction for a PMW waveform outputted from the respective PWM-type power inverting units in the corresponding phase so that each phase current between the respective PWM-type inverting units is balanced.

Claims

1. A power inverter comprising:

three or more PWM-type power inverting units which are so arranged and constructed as to be enabled to be driven in parallel;

a plurality of integrated interphase reactors , each of which is so arranged and constructed as to synthesize each of the same phase output currents of the respective PWM-type inverting units and supply the synthesized phase output current to a load; and

a plurality of current balance controllers, each of which is so arranged and constructed as to carry out a retardation correction for a PMW waveform outputted from the respective PWM-type power inverting units in the corresponding phase so that each phase current between the respective PWM-type inverting units is balanced, and wherein each of the integrated interphase reactors includes;

a magnetic core member having a plurality of juxtaposed leg portions and a plurality of coils, each coil being wound so as to interlink to a corresponding one of the leg portions of the core member, each of same instantaneous polarity indicating terminals of the coils being connected to a corresponding phase output end of each PWM-type inverting unit so that the respective coils operatively generate magnetic fluxes on the juxtaposed leg portions in mutually the same directions in response to output phase currents of the respective PWM-type power inverting units and each of the other terminals thereof being connected together to the load.

2. A power inverter as claimed in claim 1, wherein said magnetic core member of each integrated interphase reactor comprises an iron core and wherein the number of the juxtaposed leg portions of each integrated interphase reactor is the same number of the PWM-type parallel driven inverting units (N, N≧

3).

3. A power inverter as claimed in claim 2, wherein said iron core of each integrated interphase reactor has a connection leg portion integrally connected to each juxtaposed leg portion and another magnetic core juxtaposed to the connection leg portion with a gap provided against a free end of each juxtaposed leg portion and wherein a winding direction of each coil on the corresponding one of the juxtaposed leg portions of each integrated interphase reactor is the same.

4. A power inverter as claimed in claim 2, wherein said iron core of each integrated interphase reactor has a plurality of connection leg portions, each connection leg portion being integrally connected to corresponding two of the juxtaposed leg portions, and a plurality of other iron cores, each of the other iron cores being juxtaposed to a corresponding one of the connection leg portions with a gap provided against a free end of each juxtaposed leg portion and wherein each coil is wound on the corresponding two of the juxtaposed leg portions.

5. A power inverter as claimed in claim 3, which further comprises a short-circuited coil in each of said integrated interphase reactors and another leg portion juxtaposed to the juxtaposed leg portions on which the short-circuited coil is wound so that a variation in interlinkage magnetic fluxes on the remaining coils other than the short-circuit coil is suppressed.

6. A power inverter as claimed in claim 4, which further comprises a short-circuited coil in each of said integrated interphase reactors and another leg portion juxtaposed to the juxtaposed leg portions on which the short-circuited coil is wound so that a variation in interlinkage magnetic fluxes on the remaining coils other than the short-circuit coil is suppressed.

7. A power inverter as claimed in claim 5, wherein the number of N is equal to three.

8. A power inverter as claimed in claim 1, wherein each current balance controller comprises:

a plurality of current detectors, each current detector detecting a phase output current from the corresponding phase output end of the respective PWM-type power inverting units;

a calculator arranged for deriving an average value of the detected phase output currents by the current detectors;

a plurality of deviation determinators, each arranged for determining a deviation of the average value of the detected phase output currents from the corresponding one of the detected phase output currents;

a plurality of time compensation quantity calculators, each of which is arranged for determining whether the determined deviation is positive or negative and for deriving a time compensation quantity corresponding to the deviation of the average value of the detected phase output currents from the corresponding one of the detected phase output currents according to the determination of whether the determined deviation is positive or negative; and

a plurality of two-series connected waveform correctors, one of each of the two-series connected correctors thereof being arranged for delaying a rise time of a PWM waveform outputted at the corresponding phase output end of the corresponding one of the PWM-type power inverting units by the time compensation quantity when the determined deviation is positive and the other of each of the two-series connected correctors thereof being arranged for delaying a fall time of the same PWM waveform outputted at the same output phase end of the same of the PWM-type power inverting units when the determined deviation is negative.

9. A power inverter as claimed in claim 8, wherein each of the time compensation quantity calculators comprises limiters, each arranged for limiting the time compensation quantity within limit values corresponding to positive and negative constant delay time duration +,- Tbo and wherein each of the time compensation quantity calculators adds an offset signal corresponding to the positive and negative constant time durations +,- Tbo to an output signal of each of the limiters.

10. A power inverter as claimed in claim 9, which further comprises a plurality of voltage averaging circuits, each phase voltage averaging circuit selectively and sequentially sampling an output voltage of the same phase between each of the PWM-type power inverting units so as to derive an average value of the corresponding phase voltage and a plurality of dead time compensation circuits, each circuit carrying out a dead time compensation for the PWM waveform according to the derived average voltage value so that a dead time of the PWM waveform is compensated for according to the derived average voltage value.

11. A power inverter as claimed in claim 10, wherein the load comprises a three-phase induction motor.