Method and apparatus for designing an LSI layout utilizing cells having a predetermined wiring height in order to reduce wiring zones

• US 5,852,562 A
• Filed: 12/12/1995
• Issued: 12/22/1998
• Est. Priority Date: 12/13/1994
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Fukui, Masahiro, Shinomiya, Noriko, Akino, Toshiro, Toyonaga, Masahiko
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Siek, Vuthe
• Application Number:
  US08/571,130
• Time in Patent Office: 1,106 Days
• Field of Search: 364/488-491, 364/578, 395/500
• US Class Current: 716/139
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

To reduce a circuit block in area, the present invention provides an LSI layout design method having a cell changing processing for reducing a pure wiring zone in area.

By an input processing, circuit design information and cell library are entered. Then, a layout of cells arranged in a plurality of cell rows is designed by a cell placing processing. Then, the height of a wiring zone required between cell rows is estimated by a wiring zone height estimating processing. To reduce the area of a pure wiring zone other than the over-the-cell wiring zones, each of placed cells is changed, by a cell changing processing, to a cell having the same specifications and a different shape or a different terminal position. A layout of cell interconnection is designed by a wiring processing. Based on the layout thus obtained by the processings above-mentioned, a mask pattern is prepared and supplied by a mask pattern preparing processing.

Claims

1. An LSI layout design method of designing, according to circuit design information, a layout of cells and cell interconnection on a semiconductor substrate and preparing a mask pattern based on the layout thus designed, comprising:

an input processing for entering circuit design information and the information of a cell group which can be placed;

a cell placing processing for selecting cells from said cell group which can be placed, and for two-dimensionally placing said cells thus selected on a plane according to said circuit design information, thereby to design a layout of said selected cells arranged in a plurality of parallel cell rows;

a wiring zone height estimating processing for estimating, in said cell layout designed by said cell placing processing, the wiring zone height or length in a direction at a right angle to said cell rows, of a necessary wiring zone required between two adjacent cell rows for the purpose of wiring;

a cell changing processing for amending said cell layout by changing a cell placed on said cell layout designed by said cell placing processing, to a cell which has the same specifications and a different shape or a different cell terminal position and which is contained in said cell group which can be placed, thereby to reduce the area of a pure wiring zone disposed solely for the purpose of wiring, said pure wiring zone being required for assuring said wiring zone height of said necessary wiring zone, in addition to the over-the-cell wiring zones where wiring can be made on cells;

a wiring processing for designing a layout of cell interconnection according to said cell layout amended by said cell changing processing and according to said circuit design information; and

a mask pattern preparing processing for preparing a mask pattern based on said layout of cell and cell interconnection designed by said processings above-mentioned,

wherein said cell changing processing comprises;

a cell row height determining processing for obtaining a cell row height such that said wiring zone height of said necessary wiring zone is assured in said over-the-cell wiring zone;

a cell merge processing for (i) acquiring, from said information entered by said input processing relating to said cell group which can be placed, the figure information of placement and wiring of transistors of cells forming each cell row, (ii) merging a plurality of cells of one cell row or two adjacent cell rows, into one cell, and (iii) vertically or horizontally compacting the figure of placement and wiring of the transistors of said plurality of cells such that the height of each of said cell rows is equal to said cell row height obtained by said cell row height determining processing; and

a processing for changing a plurality of cells out of said cells placed by said cell placing processing, to a cell obtained by said cell merge processing.

2. An LSI layout design method according to claim 1,

wherein said cell merge processing comprises:

a zones-to-be-merged dividing processing for dividing a zone occupied by one cell row or by two adjacent columns, into a plurality of zones to be merged; and

a processing for merging, into one cell, a plurality of cells in each of said zones to be merged thus divided, and vertically or horizontally compacting the figure of placement and wiring of the transistors of said plurality of cells.

3. An LSI layout design method according to claim 1,

wherein said cell merge processing comprises:

a necessary area estimating processing for estimating the necessary area of each of P-and N-type impurity zones in at least one cell row; and

a processing for merging a plurality of cells of each cell row into one cell and vertically or horizontally compacting the figure of placement and wiring of the transistors of said plurality of cells such that the ratio of the P-type impurity zone height to the N-type impurity zone height within said cell row height obtained by said cell row height determining processing, is equal to the ratio of said P-type impurity zone necessary area to said N-type impurity zone necessary area, said necessary areas being obtained by said necessary area estimating processing.

4. An LSI layout design apparatus for designing, in an LSI design process, a layout of cells and cell interconnection on a semiconductor substrate according to circuit design information, and preparing a mask pattern based on the layout thus designed, comprising:

an input means for entering circuit design information and the information of a cell group which can be placed;

a cell placing means for selecting cells from said cell group which can be placed, and for two-dimensionally placing said cells thus selected on a plane according to said circuit design information entered by said input means, thereby to design a layout of said selected cells arranged in a plurality of parallel cell rows;

a wiring zone height estimating means for estimating, in said cell layout designed by said cell placing means, the wiring zone height or length in a direction at a right angle to said cell rows, of a necessary wiring zone required between two adjacent cell rows for the purpose of wiring;

a cell changing means for amending said cell layout by changing a cell placed on said cell layout designed by said cell placing means, to a cell which has the same specifications and a different shape or a different cell terminal position and which is contained in said cell group which can be placed, thereby to reduce the area of pure 45 wiring zone disposed solely for the purpose of wiring, said pure wiring zone being required for assuring said wiring zone height of said necessary wiring zone, in addition to the over-the-cell wiring zones where wiring can be made on cells;

a wiring means for designing a layout of cell interconnection according to said cell layout amended by said cell changing means and according to said circuit design information; and

a mask pattern preparing means for preparing a mask pattern based on said layout of cell interconnection designed by said means above-mentioned,

wherein said cell changing processing comprises;

a cell row height determining means for obtaining a cell row height such that said wiring zone height of said necessary wiring zone is assured in said over-the-cell wiring zone;

a cell merge means for (i) acquiring, from said information entered by said input means relating to said cell group which can be placed, the figure information of placement and wiring of transistors of cells forming each cell row, (ii) merging a plurality of cells of one cell row or two adjacent cell rows, into one cell, and (iii) vertically or horizontally compacting the figure of placement and wiring of the transistors of said plurality of cells such that the height of each of said cell rows is equal to said cell row height obtained by said cell row height determining means; and

a means for changing a plurality of cells out of said cells placed by said cell placing means, to a cell obtained by said cell merge means.

5. An LSI layout design apparatus according to claim 4,

wherein said cell merge means comprises:

a zones-to-be-merged dividing means for dividing a zone occupied by one cell row or two adjacent columns, into a plurality of zones to be merged; and

a means for merging, into one cell, a plurality of cells in each of said zones to be merged thus divided, and vertically or horizontally compacting the figure of placement and wiring of the transistors of said plurality of cells.

6. An LSI layout design apparatus according to claim 4,

wherein said cell merge means comprises:

a necessary area estimating means for estimating the necessary area of each of P- and N-type impurity zones in at least one cell row; and

a means for merging a plurality of cells of each cell row into one cell and vertically or horizontally compacting the figure of placement and wiring of the transistors of said plurality of cells such that the ratio of the P-type impurity zone height to the N-type impurity zone height within said cell row height obtained by said cell row height determining means, is equal to the ratio of said P-type impurity zone necessary area to said N-type impurity zone necessary area, said necessary areas being obtained by said necessary area estimating means.