Repair fuse circuit in a flash memory device

• US 5,852,580 A
• Filed: 12/29/1997
• Issued: 12/22/1998
• Est. Priority Date: 12/28/1996
• Status: Expired due to Term

• Current Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Original Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Inventors: Ha, Chang Wan
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US08/999,350
• Time in Patent Office: 358 Days
• Field of Search: 365/200, 365/225.7, 365/230.08, 365/189.05, 365/189.07
• US Class Current: 365/200
• CPC Class Codes: G11C 29/789 using non-volatile cells or latches
• CPC Class Codes: G11C 29/83 with reduced power consumption

Abstract

The repair fuse circuit of the present invention comprises a power-on reset circuit to generate first and second control signals in response to a reset pulse which is generated upon power-on; a delay circuit to generate second and fourth control signals which are delayed according to the first control signal; a gate voltage control circuit to generate a fifth control signal which is delayed according to the third control signal; a reference voltage generating circuit to generate a reference voltage in response to the fourth control signal; a fuse cell sensing and latching circuit to latch a data stored on a fuse cell in response to the fifth control signal; and an address compare circuit to generate a redundant address by comparing an output of the fuse cell sensing and latching circuit with a normal address.

Claims

1. A repair fuse circuit in a flash memory device, comprising;

a power-on reset circuit to generate first and second control signals in response to a reset pulse which is generated upon power-on;

a delay circuit to generate third and fourth control signals which are delayed according to said first control signal;

a gate voltage control circuit to generate a fifth control signal which is delayed according to said third control signal;

a reference voltage generating circuit to generate a reference voltage in response to said fourth control signal;

a fuse cell sensing and latching circuit to latch a data stored on a fuse cell in response to said fifth control signal, wherein said fuse cell sensing and latching circuit is initialized by said first and second control signals before the data is latched; and

an address compare circuit to generate a redundant address by comparing an output of said fuse cell sensing and latching circuit with a normal address.

2. The circuit of claim 1, wherein said fuse cell sensing and latching circuit comprises a fuse cell having both functions of program and erasure, a latch circuit to latch a data stored on said fuse cell and a means for initializing said latch circuit upon power-on.