Method of stress testing memory integrated circuits

• US 5,852,581 A
• Filed: 06/13/1996
• Issued: 12/22/1998
• Est. Priority Date: 06/13/1996
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Farnworth, Warren M., Cloud, Eugene H., Nevill, Leland R., Waller, William K., Beffa, Ray
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US08/663,515
• Time in Patent Office: 922 Days
• Field of Search: 365/201, 365/149
• US Class Current: 365/201
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Abstract

A memory self-stress mode capable of use during wafer burn-in such as for dynamic random access memory (DRAM) integrated circuits. A burn-in power supply voltage and ground voltage delivered to a common node of a plurality of memory cell storage capacitors and to an equilibrate node coupled to bit lines. An all row high test cycles word lines between a binary low logic level and a binary high logic level, thereby stressing the dielectric of the memory cell storage capacitors by imposing stress voltages of differing polarity. A half row high test cycles alternate word lines of a word line sequence thereby stressing undesired short circuit connections between adjacent word lines.

Claims

1. A method of stress testing a memory integrated circuit die, the method comprising:

supplying a burn-in power supply voltage and a ground voltage to each memory die of a plurality of memory die on a semiconductor wafer;

providing the burn-in power supply voltage to a cell plate common node of a memory cell storage capacitor;

providing the ground voltage to at least one bit line of a plurality of bit lines; and

turning on a cell access transistor between the bit line and a storage node of the memory cell storage capacitor, thereby allowing conduction between the bit line and the storage node of the memory cell storage capacitor, wherein turning on the cell access transistor comprises turning on alternating word lines of a word line sequence, wherein a particular word line controls a plurality of cell access transistors and turns on each cell access transistor of the plurality of cell access transistors in response to a voltage applied to the particular word line;

providing the ground voltage to the common cell plate of the memory cell storage capacitor; and

providing the burn-in power supply voltage to at least one bit line of the plurality of bit lines.

2. The method of claim 1, wherein the step of supplying a burn-in power supply voltage includes the step of detecting the burn-in power supply voltage for initiating a burn-in self-stress mode.

3. The method of claim 1, further comprising supplying a clock signal to each memory die of the plurality of memory die on the semiconductor wafer.

4. The method of claim 1, further comprising heating the semiconductor wafer comprising the plurality of memory die.

5. The method of claim 1, further comprising cooling the semiconductor wafer comprising the plurality of memory die.

6. The method of claim 1, wherein the memory integrated circuit die comprises a dynamic random access memory (DRAM).

7. A method of stress testing a memory integrated circuit die, the method comprising:

supplying a burn-in power supply voltage and a ground voltage to each memory die of a plurality of memory die on a semiconductor wafer;

providing the burn-in power supply voltage to a cell plate common node of a memory cell storage capacitor;

providing the ground voltage to at least one bit line of a plurality of bit lines;

turning on a cell access transistor between the bit line and a storage node of the memory cell storage capacitor, thereby allowing conduction between the bit line and the storage node of the memory cell storage capacitor, wherein turning on the cell access transistor comprises turning on a particular word line of a plurality of word lines, and wherein the particular word line controls a plurality of cell access transistors and turns on each cell access transistor of the plurality of cell access transistors controlled by the particular word line in response to a voltage applied to the particular word line, wherein the plurality of word lines are arranged in a word line sequence and wherein the turning on of the particular word line comprises turning on alternating word lines in the word line sequence;

providing the ground voltage to the common cell plate of the memory cell storage capacitor; and

providing the burn-in power supply voltage to at least one bit line of the plurality of bit lines.

8. A method of stress testing a memory integrated circuit die including a plurality of memory cells, a plurality of bit lines and a sequence of word lines, and a common node, with each memory cell coupled to one of the bit lines, one of the word lines, and the common node, the method comprising:

providing a burn-in voltage differential across the common node and one of the bit lines; and

turning on alternate word lines of the sequence of word lines.

9. The method of claim 8 wherein providing the burn-in voltage differential across the common node and one of the bit lines comprises:

providing a burn-in power supply voltage to the common node; and

providing a ground voltage to one of the bit lines.

10. The method of claim 8, wherein providing the burn-in voltage differential occurs after detecting a predetermined number of cycles of a clock signal.

11. The method of claim 8, further comprising:

reversing polarity of the burn-in voltage differential one or more times.

12. A method of stressing insulation in a memory integrated circuit die on a wafer, the memory integrated circuit die including a plurality of memory cells, a plurality of bit lines, a sequence of word lines, and a common node, with each memory cell coupled to one of the bit lines, to one of the word lines, and to the common node, the method comprising:

providing a burn-in voltage differential across a pair of adjacent word lines in the word line sequence to stress insulation between the adjacent word lines; and

reversing polarity of the burn-in voltage differential one or more times to further stress insulation between the adjacent word lines.

13. The method of claim 12, further comprising:

isolating the integrated circuit memory die from the burn-in voltage differential, after detecting failure of the insulation between the adjacent word lines.

14. The method of claim 12, further comprising:

providing the burn-in voltage differential across the common node and the storage node of one of the memory cells to stress insulation between the common node and the storage node; and

reversing polarity of the burn-in voltage differential one or more times to further stress insulation between the common node and the storage node.

15. The method of claim 14, further comprising:

isolating the integrated circuit memory die from the burn-in voltage differential, after detecting failure of the insulation between the common node and the storage node.

16. The method of claim 12, further comprising:

providing the burn-in voltage differential across one of the bit lines and one of the word lines to stress insulation between the one bit line and the one word line; and

reversing polarity of the burn-in voltage differential one or more times to further stress insulation between the one bit line and the one word line.

17. The method of claim 16, further comprising:

detecting failure of the insulation between the one bit line and the one word line; and

isolating the integrated circuit memory die from the burn-in voltage differential, after detecting failure of the insulation between the one bit line and the one word line.

18. A method of stressing insulation in a memory integrated circuit die on a wafer, the memory integrated circuit die including a plurality of memory cells, a plurality of bit lines, a sequence of word lines, and a common node, with each memory cell coupled to one of the bit lines, to one of the word lines, and to the common node, the method comprising:

providing a burn-in voltage differential between a pair of adjacent word lines in the sequence of word lines to stress insulation between the adjacent word lines;

reversing polarity of the burn-in voltage differential one or more times to further stress insulation between the adjacent word lines;

providing the burn-in voltage differential across the common node and the storage node of one of the memory cells to stress insulation between the common node and the storage node;

reversing polarity of the burn-in voltage differential one or more times to further stress insulation between the common node and the storage node;

providing the burn-in voltage differential across one of the bit lines and one of the word lines to stress insulation between the one bit line and the one word line; and

reversing polarity of the burn-in voltage differential one or more times to further stress insulation between the one bit line and the one word line.

19. The method of claim 18, further comprising:

detecting failure of the insulation between the adjacent word lines, the insulation between the common node and the storage node, or the insulation between the one bit line and the one word line; and

then isolating the integrated circuit memory die from the burn-in voltage differential.

20. The method of claim 18, wherein providing the differential burn-in voltage comprises:

providing a burn-in power supply voltage; and

providing a ground voltage.

21. A method of stressing insulation in a memory integrated circuit die on a wafer, the memory integrated circuit die including a plurality of memory cells, a plurality of bit lines, a sequence of word lines, and a common node, with each memory cell coupled to one of the bit lines, to one of the word lines, and to the common node, the method comprising:

detecting a predetermined number of cycles of a clock signal;

providing a burn-in voltage differential across a pair of adjacent word lines in the word line sequence, across the common node and the storage node of one of the memory cells, or across one bit line and one word line, after detecting the predetermined number of cycles of the clock signal; and

reversing polarity of the burn-in voltage differential one or more times.

22. The method of claim 21 wherein providing the burn-in voltage differential comprises:

providing a burn-in power supply voltage; and

providing a ground voltage.

23. The method of claim 21 wherein detecting the predetermined number of clock cycles of the clock signal occurs before the memory integrated circuit die is functionally tested.