Polymorphic network methods and apparatus

• US 5,852,740 A
• Filed: 10/15/1997
• Issued: 12/22/1998
• Est. Priority Date: 01/16/1991
• Status: Expired due to Fees

• Current Assignee: Mark D. Estes
• Original Assignee: Mark D. Estes
• Inventors: Estes, Mark D.
• Primary Examiner(s): Shah, Alpesh M.
• Application Number:
  US08/951,057
• Time in Patent Office: 433 Days
• Field of Search: 395/800.01, 395/800.13, 395/800.15, 395/200.3, 395/200.79, 395/200.68, 395/200.8, 395/200.5, 340/825.79, 340/825.83, 340/825.87, 340/825.03, 340/826, 370/254, 370/351, 370/402, 370/404, 370/406, 370/419
• US Class Current: 712/15
• CPC Class Codes: G06F 15/17343 wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture reconfigurable processors arrays G06F15/7867
• CPC Class Codes: G06T 17/00 Three dimensional [3D] modelling, e.g. data description of 3D objects
• CPC Class Codes: Y10S 715/966 Computer process, e.g. operation of computer

Abstract

A modular, polymorphic network interconnecting a plurality of electronically reconfigurable devices via a modular, polymorphic interconnect, to permit a fixed, physical configuration of operating hardware devices to take on a plurality of logically addressable configurations. The modular, polymorphic interconnect further permits allocation and deallocation of selected electronically reconfigurable devices for a particular logically addressable configuration. The modular, polymorphic interconnect additionally permits the logical topology of selected electronically reconfigurable devices to be configured as at least one mixed-radix, N-dimensional network. The logical topology of mixed-radix, N-dimensional networks can be dynamically changed under control for a new configuration of logical addresses for selected electronically reconfigurable devices. The modular, polymorphic interconnect also permits one or more electronically reconfigurable devices to be selected from at least one logically related set of electronically reconfigurable devices, making the resulting network system particularly well suited for a variety of purposes related to resource management.

Claims

1. A method of controlling a Gray code transition sequence using a plurality of dimensions corresponding to attributes which name a plurality of groups of related object space configurations, and a first dimension corresponding to an attribute of the Gray code transition sequence described by grouping named transitions in which the same bit position of codewords changes, comprising the steps of:

allocating a context configuration control network;

inputting, using the plurality of dimensions, data representing a particular object space configuration;

inputting the first dimension, corresponding to a particular step in the Gray code transition sequence; and

determining a bit position which changes to produce a next codeword in the Gray code transition sequence.

2. A method of controlling a Gray code transition sequence using a plurality of dimensions corresponding to attributes which name a plurality of groups of related object space configurations, and a first dimension corresponding to an attribute of the Gray code transition sequence described by a particular bit position of codewords, comprising the steps of

allocating a context configuration control network;

inputting, using the plurality of dimensions, data representing a particular object space configuration;

inputting the first dimension, corresponding to a particular bit position of a codeword for the Gray code transition sequence; and

determining if the particular bit position is a next logically adjacent for the Gray code transition sequence.