Semiconductor IC with a plurality of processing circuits which receive parallel data via a parallel data transfer circuit

• US 5,854,636 A
• Filed: 09/16/1997
• Issued: 12/29/1998
• Est. Priority Date: 04/11/1994
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Nakagawa, Tetsuya, Nakagome, Yoshinobu, Watanabe, Takao, Kiuchi, Atsushi, Ishikura, Kazuo
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): Chow, Christopher S.
• Application Number:
  US08/931,776
• Time in Patent Office: 469 Days
• Field of Search: 365/189.01, 365/230.02, 365/230.03, 382/279, 382/302, 382/303, 382/304, 345/507, 348/571
• US Class Current: 345/519
• CPC Class Codes: G06F 17/10 Complex mathematical operations function generation by table look-up G06F1/03; evaluation of elementary functions by calculation G06F7/544
• CPC Class Codes: G06F 17/15 Correlation function computation including computation of convolution operations arithmetic circuits for sum of products per se, e.g. multiply-accumulators G06F7/5443; digital filters, e.g. FIR, IIR, adaptive filters H03H17/00
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

A semiconductor integrated circuit having a two-dimensional array (MAR) and a parallel data transfer circuit (TRC) for transferring from the array data read out in parallel through data lines, in parallel to a processing circuit group (PE) by selecting the word lines of the two-dimensional memory array. The processing circuit group executing processing operations in parallel by using the data transferred from the parallel data transfer circuit. Each of the processing circuits having access to a plurality of series word lines and the data lines of the two-dimensional array through the parallel data transfer circuits. The arrangement of the parallel data transfer circuits allowing for an overlap range wherein data from each of the data lines of the memory array is available to more than one of the parallel data transfer circuits. Since the data lines of the two-dimensional memory array have the overlapped range, convolution processing operations or the like can be executed in parallel for the two-dimensional data stored in the two-dimensional memory array in a high parallelism and at a high speed.

Claims

1. A semiconductor integrated circuit comprising:

a memory cell array including a plurality of data lines, a plurality of word lines intersecting said plurality of data lines, and a plurality of memory cells disposed at desired intersections between said plurality of data lines and said plurality of word lines;

a parallel data transfer circuit coupled to first group, second group, and third group data lines of said plurality of data lines; and

first, second, and third processing circuits coupled to said parallel data transfer circuit respectively,

wherein said parallel data transfer circuit selects one of said first group, second group, and third group data lines of said plurality of data lines, and

wherein the adjoining ones of said first, second, and third processing circuits can be coupled to the same group data lines.

2. A semiconductor integrated circuit according to claim 1, wherein each of said first, second, and third processing circuits execute the processing operations by using a plurality of data which are read out to one of said plurality of data lines by selecting two or more of said plurality of word lines.

3. A semiconductor integrated circuit according to claim 2, further comprising:

a first serial access memory for storing serial data inputted from the outside and outputting said serial data in parallel to said plurality of data lines; and

a second serial access memory for transforming the output data of said plurality of processing circuits into serial data and outputting said serial data to the outside.

4. A semiconductor integrated circuit according to claim 2, wherein each of first, second, and third processing circuits executes the processing operation by using a plurality of data from said memory cell array and a predetermined constant.

5. A semiconductor integrated circuit according to claim 1, further comprising:

a first serial access memory for storing serial data inputted from the outside and outputting said serial data in parallel to said plurality of data lines; and

a second serial access memory for transforming the output data of said plurality of processing circuits into serial data and outputting said serial data to the outside.

6. A semiconductor integrated circuit according to claim 5, wherein each of first, second, and third processing circuits executes the processing operation by using a plurality of data from said memory cell array and a predetermined constant.

7. A semiconductor integrated circuit according to claim 1, wherein each of first, second, and third processing circuits executes the processing operation by using a plurality of data from said memory cell array and a predetermined constant.

8. A semiconductor integrated circuit according to claim 1, further comprising:

a first serial access memory for storing serial data inputted from the outside and outputting said serial data in parallel to said plurality of data lines; and

a second serial access memory for transforming the output data of said plurality of processing circuits into serial data and outputting said serial data to the outside.

9. A semiconductor integrated circuit according to claim 8, wherein said serial data inputted to said first serial data memory are pixel data of an image.

10. A semiconductor integrated circuit according to claim 9, further comprising:

a data memory for storing filter coefficients, wherein each of said first, second, and third processing circuits execute the filter processing operations of the image based on said pixel data and said filter coefficients.

11. A semiconductor integrated circuit comprising:

a memory cell array including a plurality of data line groups, a plurality of word lines intersecting said plurality of data line groups, and a plurality of memory cells disposed at desired intersections between said plurality of data line groups and said plurality of word lines;

a parallel data transfer circuit for transferring a plurality of data groups in parallel from said plurality of data line groups; and

a plurality of processing circuits for receiving said plurality of data groups transferred from said parallel data transfer circuit, as their input signals,

wherein said parallel data transfer circuit is enabled to transfer two or more of said plurality of data groups to each of said plurality of processing circuits by sequentially selecting two or more of said plurality of data line groups and coupling to each of said plurality of processing circuits and wherein the adjoining ones of said plurality of processing circuits can input the same data group from the same data line groups.

12. A semiconductor integrated circuit according to claim 11, wherein each of said plurality of processing circuits execute the processing operations by using the plurality of data groups which are read out to one of said plurality of data line groups by selecting two or more of said plurality of word lines.

13. A semiconductor integrated circuit according to claim 12, further comprising:

a first serial access memory for storing serial data inputted from the outside and outputting said serial data in parallel to said plurality of data line groups; and

a second serial access memory for transforming the output data of said plurality of processing circuits into serial data and outputting said serial data to the outside.

14. A semiconductor integrated circuit according to claim 12, wherein each of said plurality of processing circuits executes the processing operation by using said plurality of data groups from said memory cell array and a predetermined constant.

15. A semiconductor integrated circuit according to claim 11, further comprising:

a first serial access memory for storing serial data inputted from the out side and outputting said serial data in parallel to said plurality of data line groups; and

a second serial access memory for transforming the output data of said plurality of processing circuits into serial data and outputting said serial data to the outside.

16. A semiconductor integrated circuit according to claim 15, wherein each of said plurality of processing circuits executes the processing operation by using said plurality of data groups from said memory cell array and a predetermined constant.

17. A semiconductor integrated circuit according to claim 11, wherein each of said plurality of processing circuits executes the processing operation by using said plurality of data groups from said memory cell array and a predetermined constant.

18. A semiconductor integrated circuit comprising:

first and second memory cell arrays each of which including a plurality of data lines, a plurality of word lines intersecting said plurality of data lines, and a plurality of memory cells disposed at desired intersections between said plurality of data lines and said plurality of word lines;

a first parallel data transfer circuit coupled to first group, second group, and third group data lines of said plurality of data lines of said first memory cell array;

a second parallel data transfer circuit coupled to first group, second group, and third group data lines of said plurality of data lines of said second memory cell array; and

first, second, and third processing circuits coupled to said first and second parallel data transfer circuits,

wherein said first parallel data transfer circuit selects one of said first group, second group, and third group data lines of said plurality of data lines of said first memory cell array,

wherein the adjoining ones of said first, second, and third processing circuits can couple to the same data lines of said first memory cell array, and

wherein said second parallel data transfer circuit selects one of said first group, second group, and third group data lines of said plurality of data lines of said second memory cell array.

19. A semiconductor integrated circuit according to claim 18,

wherein said processing operation uses two-dimensional data stored in said first memory cell array.

20. A semiconductor integrated circuit according to claim 19, further comprising:

a first serial access memory for storing serial data inputted from the outside and outputting said serial data in parallel to said plurality of data lines of said first memory cell array;

a second serial access memory for storing serial data inputted from the outside and outputting said serial data in parallel to said plurality of data lines of said second memory cell array; and

,

a third serial access memory for transforming the output data of said plurality of processing circuits into serial data and outputting said serial data to the outside.

21. A semiconductor integrated circuit according to claim 20,

wherein said serial data inputted to said first serial data access memory are pixel data of a reference image;

and,

said serial data inputted to said second serial data access memory are pixel data of an input image.

22. A semiconductor integrated circuit according to claim 21, further comprising:

third and fourth memory cell arrays each of which includes a plurality of data lines, a plurality of word lines intersecting said plurality of data lines, and a plurality of memory cells disposed at desired intersections between said plurality of data lines and said plurality of word lines;

wherein each of said plurality of data lines of said third memory cell array is coupled to each of said plurality of data lines of said first memory cell array;

wherein each of said plurality of data lines of said fourth memory cell array is coupled to each of said plurality of data lines of said second memory cell array; and

,

wherein said processing circuits execute the processing operation while said third and fourth memory cell arrays store data for the following operation.

23. A semiconductor integrated circuit according to claim 22,

wherein said processing circuits process the moving vector of a moving image by using pixel data of an input image and a reference image.

24. A semiconductor integrated circuit comprising:

first and second memory cell arrays each of which including a plurality of data line groups, a plurality of word lines intersecting said plurality of data line groups, and a plurality of memory cells disposed at desired intersections between said plurality of data line groups and said plurality of word lines;

a first parallel data transfer circuit for transferring a plurality of first data groups in parallel from said plurality of data line groups of said first memory cell array;

a second parallel data transfer circuit for transferring a plurality of second data groups in parallel from said plurality of data line groups of said second memory cell array, and a plurality of processing circuits for receiving said plurality of first and second data groups transferred from said first and second parallel data transfer circuits, as their input signals,

wherein said first parallel data transfer circuit is enabled to transfer two or more of said plurality of first data groups to each of said plurality of processing circuits by sequentially selecting two or more of said plurality of first data line groups and coupling to each of said plurality of processing circuits, wherein the adjoining ones of said plurality of processing circuits can input the same data group from the same data line groups, and

wherein said second parallel data transfer circuit is enabled to transfer two or more of said plurality of second data groups to each of said plurality of processing circuits by sequentially selecting two or more of said plurality of second data line groups and coupling to each of said plurality of processing circuits.

25. A semiconductor integrated circuit according to claim 24, further comprising:

a first serial access memory for storing serial data inputted from the outside and outputting said serial data in parallel to said plurality of data lines of said first memory cell array;

a second serial access memory for storing serial data inputted from the outside and outputting said serial data in parallel to said plurality of data lines of said second memory cell array; and

,

a third serial access memory for transforming the output data of said plurality of processing circuits into serial data and outputting said serial data to the outside.

26. A semiconductor integrated circuit according to claim 25,

wherein said serial data inputted to said first serial data access memory are pixel data of a reference image;

and,

said serial data inputted to said second serial data access memory are pixel data of an input image.

27. A semiconductor integrated circuit according to claim 26, further comprising:

third and fourth memory cell arrays each of which includes a plurality of data lines, a plurality of word lines intersecting said plurality of data lines, and a plurality of memory cells disposed at desired intersections between said plurality of data lines and said plurality of word lines;

each of said plurality of data lines of said third memory cell array couples to each of said plurality of data lines of said first memory cell array;

each of said plurality of data lines of said fourth memory cell array couples to each of said plurality of data lines of said second memory cell array; and

,

wherein said processing circuits execute the processing operation while said third and fourth memory cell arrays store data for the following operation.

28. A semiconductor integrated circuit according to claim 27,

said processing circuits process the moving vector of a moving image by using pixel data of an input image and a referenced image.