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Circuit partitioning technique for use with multiplexed inter-connections

  • US 5,854,752 A
  • Filed: 01/19/1996
  • Issued: 12/29/1998
  • Est. Priority Date: 01/19/1996
  • Status: Expired due to Term
First Claim
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1. A method for emulating a logic circuit in a plurality of programmable logic devices, comprising the steps of:

  • partitioning a representation of said logic circuit into a plurality of logic blocks, in accordance with a single cost constraint, said cost constraint including functions of the number of logic gates and the number of pins of each logic, each logic block having a plurality of logic gates and a plurality of pins for connecting said logic block with other logic blocks in said plurality of logic blocks; and

    assigning each of said logic blocks to be implemented on one of said programmable logic device;

    wherein said cost constraint is given by;

    
    
    space="preserve" listing-type="equation">ƒ

    (G.sub.i,cP.sub.i)≦

    G.sub.maxwhere ƒ

    is a function of the quantities Gi and cPi, Gi being the number of logic gates in said logic block Gmax being said predetermined number of logic gates, c being a weighting factor expressing a cost of a pin in terms of a logic gate, and Pi being the number of pins in said logic block.

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