Circuit partitioning technique for use with multiplexed inter-connections

• US 5,854,752 A
• Filed: 01/19/1996
• Issued: 12/29/1998
• Est. Priority Date: 01/19/1996
• Status: Expired due to Term

• Current Assignee: Mentor Graphics Corporation (Siemens AG)
• Original Assignee: IKOS Systems Incorporated (Siemens AG)
• Inventors: Agarwal, Anant
• Primary Examiner(s): Voeltz, Emanuel Todd
• Assistant Examiner(s): TRAMMELL, JAMES P
• Application Number:
  US08/588,649
• Time in Patent Office: 1,075 Days
• Field of Search: 364/488-491, 364/578, 395/500
• US Class Current: 716/116
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

A method for partitioning a logic circuit is provided for emulation under a virtual wires method using programmable logic devices. Because a virtual wires systems replace pin constraints by a corresponding gate constraint, partitioning for a virtual wires system applies novel constraints and algorithms. In one embodiment, partitioning is provided under a "flat mincut" approach in conjunction with a virtual wire cost constraint. In another embodiment, partitioning is provided under a "hierarchical mincut" in conjunction with a virtual wire cost constraint.

Claims

1. A method for emulating a logic circuit in a plurality of programmable logic devices, comprising the steps of:

partitioning a representation of said logic circuit into a plurality of logic blocks, in accordance with a single cost constraint, said cost constraint including functions of the number of logic gates and the number of pins of each logic, each logic block having a plurality of logic gates and a plurality of pins for connecting said logic block with other logic blocks in said plurality of logic blocks; and

assigning each of said logic blocks to be implemented on one of said programmable logic device;

wherein said cost constraint is given by;

space="preserve" listing-type="equation">ƒ

(G.sub.i,cP.sub.i)≦

G.sub.max

where ƒ

is a function of the quantities G_i and cP_i, G_i being the number of logic gates in said logic block G_max being said predetermined number of logic gates, c being a weighting factor expressing a cost of a pin in terms of a logic gate, and P_i being the number of pins in said logic block.

2. A method as in claim 1, wherein said cost constraint compares a cost function against a predetermined number of logic gates, said cost function being, for each block, a function of the number of logic gates in said logic block and the number of pins in said logic block.

3. A method as in claim 1, wherein said cost constraint is given by:

space="preserve" listing-type="equation">G.sub.i +cP.sub.i ≦

G.sub.max.

4.

4. A method as in claim 1, wherein said pins in said logic block include both input pins and output pins, and wherein said cost function assigns a first cost to each input pin and a second cost to each output pin.

5. A method as in claim 4, wherein said cost assigned to said output pin is proportional to the number of input pins coupled to said output pin outside of said logic block.

6. A method as in claim 1, wherein when a pin carries a signal making a plurality of transitions within a reference clock period, said pin contributes a cost to said cost function in proportion to said plurality of transitions.

7. A method as in claim 1 wherein, prior to said step of partitioning, said method includes the step of preclustering logic elements of said representation into clusters of logic elements, each cluster being formed in accordance with a cluster size constraint on a cluster function, said cluster size constraint being expressed in terms of a number of logic gates.

8. A method as in claim 7, wherein said cluster function comprises a fraction of said cost function.

9. A method as in claim 1 wherein, prior to said step of partitioning, said method includes the step of optimizing timing, said step of optimizing timing identifying critical signal paths in said logic circuit and grouping logic elements in said critical path into logic modules having pins of minimized costs.

10. A method as in claim 1, wherein, for each pin, said cost function associates a cost to said pin in proportion to the number of unique logic blocks to which said pin is connected.

11. A method as in claim 1, further including the step of restructuring logic elements associated with said pins to minimize fan-out for output pins among said pins.

12. A method as in claim 1, wherein said cost function is a function of two or more variables associated with the number of logic circuit elements in a logic block, said variables selected from the group of:

(a) the number of logic gates in said logic block, (b) the number of flip-flops in said logic block, (c) the number of pins in said logic block, and (d) the number of memory elements in said logic block.

13. A method as in claim 12, wherein said cost function is expressed in terms of multiples of logic gates.

14. A method as in claim 12, wherein said cost function associates with each of said memory elements a cost expressed in logic gates.

15. A method as in claim 12, wherein said cost function associates with each of said memory elements a cost proportional to the number of address and data lines coupled to said memory element.

16. A method as in claim 12, wherein said cost function associates with each of said memory elements a cost C(A,D) given by:

space="preserve" listing-type="equation">C(A,D)=nA+mD

where A and D are the number of address lines and the number of data lines coupled to said memory element, respectively, and n and m are constants.

17. A method as in claim 1, wherein said cost function assigns a higher cost to pins coupling said logic circuit to a circuit external to said logic circuit.

18. A method as in claim 1, wherein said logic circuit includes a number of timing domains, each timing domain receiving a different clock signal, said cost function assigning a different cost to pins connecting logic elements of different timing domains than pins connecting logic elements of the same timing domain.

19. A method as in claim 1, wherein said step of partitioning is performed in accordance with a flat mincut algorithm.

20. A method as in claim 1, wherein said step of partitioning is performed in accordance with a hierarchical mincut algorithm.

21. A method as in claim 20, wherein said hierarchical mincut algorithm applies a flat mincut algorithm to a given logic block not satisfying a termination constraint, prior to recursively applying said hierarchical mincut algorithm to portions of said given logic block.

22. A method as in claim 1 wherein said representation is a netlist representation.