Circuit partitioning technique for use with multiplexed inter-connections
First Claim
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1. A method for emulating a logic circuit in a plurality of programmable logic devices, comprising the steps of:
- partitioning a representation of said logic circuit into a plurality of logic blocks, in accordance with a single cost constraint, said cost constraint including functions of the number of logic gates and the number of pins of each logic, each logic block having a plurality of logic gates and a plurality of pins for connecting said logic block with other logic blocks in said plurality of logic blocks; and
assigning each of said logic blocks to be implemented on one of said programmable logic device;
wherein said cost constraint is given by;
space="preserve" listing-type="equation">ƒ
(G.sub.i,cP.sub.i)≦
G.sub.maxwhere ƒ
is a function of the quantities Gi and cPi, Gi being the number of logic gates in said logic block Gmax being said predetermined number of logic gates, c being a weighting factor expressing a cost of a pin in terms of a logic gate, and Pi being the number of pins in said logic block.
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Abstract
A method for partitioning a logic circuit is provided for emulation under a virtual wires method using programmable logic devices. Because a virtual wires systems replace pin constraints by a corresponding gate constraint, partitioning for a virtual wires system applies novel constraints and algorithms. In one embodiment, partitioning is provided under a "flat mincut" approach in conjunction with a virtual wire cost constraint. In another embodiment, partitioning is provided under a "hierarchical mincut" in conjunction with a virtual wire cost constraint.
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Citations
22 Claims
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1. A method for emulating a logic circuit in a plurality of programmable logic devices, comprising the steps of:
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partitioning a representation of said logic circuit into a plurality of logic blocks, in accordance with a single cost constraint, said cost constraint including functions of the number of logic gates and the number of pins of each logic, each logic block having a plurality of logic gates and a plurality of pins for connecting said logic block with other logic blocks in said plurality of logic blocks; and assigning each of said logic blocks to be implemented on one of said programmable logic device; wherein said cost constraint is given by;
space="preserve" listing-type="equation">ƒ
(G.sub.i,cP.sub.i)≦
G.sub.maxwhere ƒ
is a function of the quantities Gi and cPi, Gi being the number of logic gates in said logic block Gmax being said predetermined number of logic gates, c being a weighting factor expressing a cost of a pin in terms of a logic gate, and Pi being the number of pins in said logic block. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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Specification