Method of and apparatus for testing semiconductor memory

• US 5,854,796 A
• Filed: 05/21/1997
• Issued: 12/29/1998
• Est. Priority Date: 05/29/1996
• Status: Expired due to Fees

• Current Assignee: Advantest Corporation
• Original Assignee: Advantest Corporation
• Inventors: Sato, Shinya
• Primary Examiner(s): Canney, Vincent P.
• Application Number:
  US08/861,344
• Time in Patent Office: 587 Days
• Field of Search: 371/21.1, 371/21.2, 371/21.4, 371/21.5, 371/21.6, 365/201
• US Class Current: 714/718
• CPC Class Codes: G01R 31/31935 Storing data, e.g. failure memory
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair

Abstract

A failure analysis memory for storing failure information representative of a test result of a semiconductor memory under test is divided into a plurality of blocks with compacted addresses, and a compaction memory having areas corresponding respectively to the blocks of the failure analysis memory is prepared. Data indicative of a failure cell in any one of the blocks of the failure analysis memory is written in an area of the compaction memory which corresponds to the any one of the blocks. Minimum and maximum addresses of addresses at which failure cells are present in the blocks are determined, and failure data is read from the failure analysis memory in a range between the minimum and maximum addresses of each of the blocks, which correspond to the areas of the compaction memory which store the data indicative of a failure cell.

Claims

1. A method of testing a semiconductor memory, comprising the steps of:

dividing a failure analysis memory for storing failure information representative of a test result of a semiconductor memory under test, into a plurality of blocks with compacted addresses;

preparing a compaction memory having areas corresponding respectively to the blocks of the failure analysis memory;

writing data indicative of a failure cell in any one of the blocks of the failure analysis memory, in an area of said compaction memory which corresponds to said any one of the blocks;

determining minimum and maximum addresses of addresses at which failure cells are present in said blocks; and

reading failure data from the failure analysis memory in a range between the minimum and maximum addresses of each of the blocks, which correspond to the areas of said compaction memory which store the data indicative of a failure cell.

2. An apparatus for testing a semiconductor memory, comprising:

a failure analysis memory divided into a plurality of blocks with compacted addresses for storing failure information representative of a test result of a semiconductor memory under test;

a compaction memory having areas corresponding respectively to the blocks of the failure analysis memory;

data writing means for writing data indicative of a failure cell in any one of the blocks of the failure analysis memory, in an area of said compaction memory which corresponds to said any one of the blocks;

minimum address storing means and maximum address storing means for storing a minimum address and a maximum address, respectively, of addresses at which failure cells are present in said blocks;

first and second address comparing means for comparing a readout address of each of the blocks of said failure analysis memory with the minimum address stored in said minimum address storing means and the maximum address stored in said maximum address storing means;

means for storing said readout address in the minimum address storing means if said readout address is smaller than said minimum address and failure data of said failure analysis memory at said readout address represents a failure address;

means for storing said readout address in the maximum address storing means if said readout address is greater than said maximum address and failure data of said failure analysis memory at said readout address represents a failure address; and

means for reading failure data from said failure analysis memory in a range between the minimum and maximum addresses of each of the blocks, which are stored in the minimum and maximum address storing means.

3. An apparatus according to claim 2, wherein each of said minimum address storing means and said maximum address storing means comprises a register.