BiCMOS devices

• US 5,856,695 A
• Filed: 07/20/1992
• Issued: 01/05/1999
• Est. Priority Date: 10/30/1991
• Status: Expired due to Term

• Current Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Ito, Akira, Church, Michael David
• Primary Examiner(s): Tran, Minh-Loan
• Assistant Examiner(s): WILLIAMS, ALEXANDER O
• Application Number:
  US07/917,635
• Time in Patent Office: 2,360 Days
• Field of Search: 257/370, 257/378, 257/401, 257/408, 257/335, 257/328, 437/31
• US Class Current: 257/370
• CPC Class Codes: G05F 3/30 Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities G05F3/26 takes precedence
• CPC Class Codes: G11C 27/026 associated with an amplifier G11C27/028 takes precedence
• CPC Class Codes: H01L 21/8249 Bipolar and MOS technology
• CPC Class Codes: H01L 27/0214 for internal polarisation, e.g. I2L
• CPC Class Codes: H01L 27/0623 in combination with bipolar transistors
• CPC Class Codes: H01L 27/0635 in combination with bipolar transistors and diodes, or resistors, or capacitors
• CPC Class Codes: H03F 1/523 for amplifiers using field-effect devices H03F1/526 takes precedence
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 3/505 with field-effect devices
• CPC Class Codes: H03G 1/0082 using bipolar transistor-type devices
• CPC Class Codes: H03K 17/223 in field-effect transistor switches
• CPC Class Codes: H03K 5/15 Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors distributing, switching or gating arrangements H03K17/00
• CPC Class Codes: H03M 1/162 the steps being performed sequentially in a single stage, i.e. recirculation type H03M1/161 takes precedence
• CPC Class Codes: H03M 1/365 the voltage divider being a single resistor string

Abstract

A BiCMOS process which provides both low voltage (digital) and high voltage (analog) CMOS devices. The high voltage NMOS devices have a compensated drain formed by the NPN and PNP base implants. The PNP base plus the high voltage NMOS drain carrier concentrations are both optimized by adjustment of the two variables N base implant dose and P base implant dose; this determines the NPN base carrier concentration which turns out to provide good NPN characteristics. Low voltage NMOS source and drain implants employ a higher dose and may also be used for the high voltage NMOS source. The NPN emitter doping may also be used for a contact to the high voltage NMOS drain contact.

Claims

1. An integrated circuit, comprising:

(a) a semiconductor layer;

(b) NPN transistors formed in said layer;

(c) PNP transistors formed in said layer; and

(d) first NMOS transistors with sources and drains formed in said layer, said first NMOS transistors with drains having p-type and n-type dopants and characterized by a dopant concentration equal to the dopant concentration of the base dopants of said PNP transistors minus the dopant concentration of the base dopants of said NPN transistors.

2. The integrated circuit of claim 1, wherein:

(a) said doping profile of said NMOS transistors drain has a maximum dopant concentration spaced away from the surfaces of said layer.

3. The integrated circuit of claim 1, wherein:

(a) sources of said first NMOS transistors are more heavily doped than said drains.

4. The integrated circuit of claim 1, further comprising:

(a) PMOS transistors with sources and drains formed in said layer; and

(b) second NMOS transistors with sources and drains formed in said layer, said second NMOS transistors having sources and drains of doping profile equal to the doping profile of said sources of said first NMOS transistors.