Method for automatically routing circuits of very large scale integration (VLSI)

• US 5,856,927 A
• Filed: 05/01/1995
• Issued: 01/05/1999
• Est. Priority Date: 05/01/1995
• Status: Expired due to Fees

• Current Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Original Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Inventors: Markosian, Ara, Greidinger, Jacob, Hartoog, Mark R., Fawcett, Christine, Sakhamuri, Prasad, Gelfund, Eugenia
• Primary Examiner(s): LOUIS JACQUES, JACQUES H
• Application Number:
  US08/432,236
• Time in Patent Office: 1,345 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 395/500, 395/800, 395/13, 395/921, 371/1, 257/211, 257/210, 257/206, 257/909, 257/204, 257/369, 438/598, 327/565, 327/564
• US Class Current: 716/122
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Abstract

An automated routing tool for routing interconnections between circuit elements, standard cells and/or cell blocks of cell-based designs which incorporates the best features of both currently known gate array routing techniques with currently known cell-based routing techniques. The invention eliminates the disadvantages of permitting the detailed router to adjust the relative positions of the circuit elements, standard cells and/or cell blocks during the detailed routing process. The method employs a topology manager which iteratively compacts the circuit topology while at the same time optimizing the routing of the interconnections among the circuit elements, standard cells and/or cell blocks of the circuit design. The method employs bin-based global routing, which identifies expandable boundaries and which provides input to a compaction routine which expands or contracts the expandable areas in accordance with the result of the global routing process. The detailed routing step is not performed until after the relative positions of the circuit elements, cells and/or cell blocks have been already fixed.

Claims

1. A method of automatically routing interconnections among a plurality of circuit elements comprising a circuit, the circuit elements having one or more connectors, the interconnections defined by a netlist, the method comprising the steps of:

determining initial placement of the circuit elements;

globally routing all nets of the netlist losing expandable boundaries, wherein said expandable boundaries comprise expandable physical regions including bin boundaries coextensive with channel spaces through which nets may be routed;

moving the circuit elements in accordance with the results of said step of globally routing;

if the moving of the circuit elements by said step of moving is greater than a predetermined amount;

reputing said steps of globally routing and moving;

otherwise, globally routing all nets of the netlist using no expandable boundaries;

routing all nets of the netlist using a detailed router; and

generating an output representative of the process layers for manufacturing the circuit.

2. The method of claim 1 further comprising the step of setting constraints on the movement of the circuit elements.

3. The method of claim 1 further comprising the step of prerouting one or more of the nets.

4. The method of claim 3, further comprising the step of setting constraints on the movement of the circuit elements.

5. A method of automatically routing interconnections among a plurality of elements on an integrated circuit comprising the steps of:

obtaining the initial element placement;

globally routing a plurality of said interconnections using expandable boundaries, wherein said expandable boundaries comprise expandable physical regions including bin boundaries coextensive with channel spaces through which nets may be routed;

moving said elements in accordance with the results of said step of globally routing;

repeating said steps of globally routing and moving until the movement of said elements pursuant to said step of moving is not greater than a predetermined amount; and

globally routing a plurality of said interconnections using no expandable boundaries.

6. The method of claim 5, further comprising the step of using a detailed router to route said interconnections subsequent to the step of globally routing said interconnections using no expandable boundaries.

7. The method of claim 6, further comprising the step of generating an output representative of the process layers for manufacturing the circuit, said step performed subsequent to said step of using a detailed router.

8. The method of claim 5, wherein the step of moving moves said elements in accordance with the minimum capacities specified for the expandable boundaries.

9. The method of claim 8, wherein said step of moving further moves said elements in accordance with any constraints input by the user of said method, said constraints entered by said user prior to said step of moving.

10. The method of claim 5, further comprising the step of prerouting at least one interconnection prior to the step of globally routing using expandable boundaries, so that said prerouted interconnections are not re-routed during said step of global routing using expandable boundaries.

11. The method of claim 10, further comprising the step of prerouting at least one interconnection prior to the step of globally routing using no expandable boundaries, so that said prerouted interconnections are not re-routed during said step of global routing using no expandable boundaries.

12. The method of claim 5, wherein the step of obtaining the initial element placement comprises obtaining the initial element placement from a netlist generated by an element placement method.

13. The method of claim 5, further comprising, between the step of globally routing using expandable boundaries and the step of moving, the steps of:

generating a grid of bin boundaries over the element placement of the present iteration;

identifying all expandable bin boundaries and areas; and

logically routing said interconnections through expandable and non-expandable boundaries while optimizing the cost of said routing.

14. The method of claim 13, further comprising between the step of logically routing said interconnections and the step of moving, the steps of:

adding sufficient tracks to said expandable areas on which overflows in capacity exist; and

reducing the number of tracks in each expandable area to minimum capacity without creating overflows on any other expandable or non-expandable area.

15. The method of claim 14, further comprising between the step of reducing the number of tracks in each expandable area and the step of moving, the step of determining the minimum tracks necessary for each expandable area, said determination useable by said method during step of moving.

16. An apparatus for automatically routing interconnections among a plurality of elements on an integrated circuit, said apparatus comprising:

means for obtaining the initial element placement;

means for globally routing a plurality of said interconnections using expandable boundaries, wherein said expandable boundaries comprise expandable physical regions including bin boundaries coextensive with channel spaces through which nets may be routed;

means for moving said elements in accordance with the results of said step of globally routing;

means for repeating said global routing and moving until the movement of said elements during a single iteration of said moving is not greater than a predetermined amount; and

means for globally routing a plurality of said interconnections using no expandable boundaries.

17. The apparatus of claim 16, further comprising:

means for generating a grid of bin boundaries over the element placement of the present iteration;

means for identifying all expandable bin boundaries and areas;

means for logically routing said interconnections through expandable and non-expandable boundaries while optimizing the cost of said routing;

means for adding sufficient tracks to said expandable areas on which overflows in capacity exist, thereby eliminating overflows;

means for reducing the number of tracks in each expandable area to minimum capacity without creating overflows on any other expandable or non-expandable area; and

means for determining the minimum tracks necessary for each expandable area, said determination useable by said step of moving.

18. A computer program product comprising a computer-usable medium having computer-readable code embodied therein for automatically routing interconnections among a plurality of elements on an integrated circuit, the computer-readable code comprising:

an initial placement module, which is configured to obtain the initial element placement;

a first global routing module, which is configured to globally route a plurality of said interconnections using expandable boundaries, wherein said expandable boundaries comprise expandable physical regions including bin boundaries coextensive with channel spaces through which nets may be routed;

a movement module, which is configured to move said elements in accordance with the results from said first global routing module;

an iteration module, which is configured to repeat the procedures dictated by said first global routing module and said movement module until the involvement of said components during an iteration of said first global routing module and said movement module is not greater than a predetermined amount; and

a second global routing module, which is configured to globally route a plurality of said interconnections using no expandable boundaries.

19. The computer program product of claim 18, further comprising:

a detailed router module, which is configured to route said interconnections subsequent to the global routing of said interconnections using no expandable boundaries; and

an output generation module, which is configured to generate an output representative of the process layers for manufacturing the circuit.

20. The computer program product of claim 19, further comprising a prerouting module, which is configured to permit the prerouting at least one interconnection prior to the step of globally routing using expandable boundaries, so that said prerouted interconnections are not re-routed during the remainder of the routing process.