High speed single chip digital video network apparatus

• US 5,856,975 A
• Filed: 12/08/1994
• Issued: 01/05/1999
• Est. Priority Date: 10/20/1993
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Desai, Sanjay, Rostoker, Michael D., Daane, John P., Stelliga, D. Tony
• Primary Examiner(s): HSU, ALPUS
• Application Number:
  US08/354,682
• Time in Patent Office: 1,489 Days
• Field of Search: 348/7, 348/12, 348/13, 348/14, 348/16, 348/17, 348/19, 348/384, 348/423, 348/426, 348/441, 348/461, 348/465, 348/467, 348/469, 348/845, 348/845.2, 364/514 R, 364/514 A, 364/514 C, 370/357, 370/360, 370/395, 370/396, 370/400, 370/401, 370/402, 370/403, 370/404, 370/405, 370/406, 370/407, 370/408, 370/410, 370/419, 370/420, 370/421, 370/428, 370/465 , 370/466, 370/467, 370/471, 370/474, 370/522
• US Class Current: 370/395.64
• CPC Class Codes: G06F 13/128 for dedicated transfers to a network for protocol converters G06F13/387
• CPC Class Codes: H04L 12/5602 Bandwidth control in ATM Networks, e.g. leaky bucket
• CPC Class Codes: H04L 2012/5613 Bus (including DQDB)
• CPC Class Codes: H04L 2012/5614 User Network Interface
• CPC Class Codes: H04L 2012/5615 Network termination, e.g. NT1, NT2, PBX
• CPC Class Codes: H04L 2012/5616 Terminal equipment, e.g. codecs, synch.
• CPC Class Codes: H04L 2012/5628 Testing
• CPC Class Codes: H04L 2012/5632 Bandwidth allocation
• CPC Class Codes: H04L 2012/5635 Backpressure, e.g. for ABR
• CPC Class Codes: H04L 2012/5636 Monitoring or policing, e.g. compliance with allocated rate, corrective actions
• CPC Class Codes: H04L 2012/5637 Leaky Buckets
• CPC Class Codes: H04L 2012/5638 Services, e.g. multimedia, GOS, QOS
• CPC Class Codes: H04L 2012/5647 Cell loss
• CPC Class Codes: H04L 2012/5652 Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
• CPC Class Codes: H04L 2012/5653 using the ATM adaptation layer [AAL]
• CPC Class Codes: H04L 2012/5664 Support of Video, e.g. MPEG
• CPC Class Codes: H04L 2012/5665 Interaction of ATM with other protocols
• CPC Class Codes: H04L 43/00 Arrangements for monitoring or testing data switching networks
• CPC Class Codes: H04L 43/0817 by checking functioning
• CPC Class Codes: H04L 43/0852 Delays
• CPC Class Codes: H04L 43/0894 : Packet rate
• CPC Class Codes: H04L 43/10 : Active monitoring, e.g. heartbeat, ping or trace-route
• CPC Class Codes: H04L 43/106 : using time related information in packets, e.g. by adding timestamps
• CPC Class Codes: H04L 45/745 : Address table lookup; Address filtering
• CPC Class Codes: H04L 47/10 : Flow control; Congestion control
• CPC Class Codes: H04L 47/11 : Identifying congestion
• CPC Class Codes: H04L 47/263 : Rate modification at the source after receiving feedback
• CPC Class Codes: H04L 47/43 : Assembling or disassembling of packets, e.g. segmentation and reassembly [SAR]
• CPC Class Codes: H04L 49/20 : Support for services
• CPC Class Codes: H04L 49/30 : Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 49/3009 : Header conversion, routing tables or routing tags
• CPC Class Codes: H04L 49/3081 : ATM peripheral units, e.g. policing, insertion or extraction
• CPC Class Codes: H04L 49/501 : Overload detection
• CPC Class Codes: H04L 49/555 : Error detection
• CPC Class Codes: H04L 49/557 : Error correction, e.g. fault recovery or fault tolerance
• CPC Class Codes: H04L 49/90 : Buffering arrangements
• CPC Class Codes: H04L 49/901 : using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9094 : Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element
• CPC Class Codes: H04N 19/00 : Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
• CPC Class Codes: H04N 19/42 : characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/61 : in combination with predictive coding
• CPC Class Codes: H04N 19/70 : characterised by syntax aspects related to video coding, e.g. related to compression standards
• CPC Class Codes: H04N 21/2381 : Adapting the multiplex stream to a specific network, e.g. an Internet Protocol [IP] network transmission of MPEG streams over ATM H04L12/5601
• CPC Class Codes: H04N 21/4381 : Recovering the multiplex stream from a specific network, e.g. recovering MPEG packets from ATM cells transmission of MPEG streams over ATM H04L12/5601
• CPC Class Codes: H04N 21/6137 : involving transmission via a telephone network, e.g. POTS
• CPC Class Codes: H04N 21/64307 : ATM
• CPC Class Codes: H04N 21/6473 : Monitoring network processes errors for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: H04N 21/64738 : Monitoring network characteristics, e.g. bandwidth, congestion level data switched network analysis H04L41/14; monitoring functioning in data switched networks H04L43/0817; flow control in packet networks H04L47/10
• CPC Class Codes: H04N 21/64792 : Controlling the complexity of the content stream, e.g. by dropping packets intermediate media network packet handling H04L65/765; proxy provisioning conversion or adaptation for reducing the amount or size of exchanged application data H04L67/5651; negotiation of resources in wireless networks H04W28/16
• CPC Class Codes: H04Q 11/0478 : Provisions for broadband connections
• CPC Class Codes: H04Q 2213/13034 : A/D conversion, code compression/expansion
• CPC Class Codes: H04Q 2213/13097 : Numbering, addressing
• CPC Class Codes: H04Q 2213/13141 : Hunting for free outlet, circuit or channel
• CPC Class Codes: H04Q 2213/13174 : Data transmission, file transfer
• CPC Class Codes: H04Q 2213/13204 : Protocols
• CPC Class Codes: H04Q 2213/13216 : Code signals, frame structure
• CPC Class Codes: H04Q 2213/13296 : Packet switching, X.25, frame relay
• CPC Class Codes: H04Q 2213/13322 : Integrated circuits
• CPC Class Codes: H04Q 2213/13332 : Broadband, CATV, dynamic bandwidth allocation
• CPC Class Codes: H04Q 2213/13353 : Routing table, map memory
• CPC Class Codes: Y02D 30/50 : in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A high speed digital video network apparatus is implemented on a single integrated circuit chip, and includes a network protocol processing system interconnection, compression/decompression circuits, and encoder/decoder circuits. The interconnection includes a packet conversion logic which converts between a network protocol, such as Asynchronous Transfer Mode (ATM) packets, and the data protocol used to handle large data streams, such as Motion Picture Experts Group (MPEG) packets. The interconnection further includes a Virtual Channel Memory (VCM) for storing ATM cells for segmentation and reassembly, a Direct Memory Access (DMA) controller for connecting the VCR to the compression/decompression circuits, a Parallel Cell Interface (PCI) for connecting the VCM to an ATM network, a Pacing Rate Unit (PCU) for automatically reducing the maximum transmission rate in response to a sensed congestion condition in the network, and a Reduced Instruction Set Computer (RISC) microprocessor for controlling the DMA controller and transfers between the memory, a host and the ATM network, for performing segmentation and reassembly of Conversion Sublayer Payload Data Units (CD-PDUs), and for performing conversion between the ATM Protocol and the MPEG protocol. The compression/decompression and decoder/encoder circuits may utilize MPEG to compress digitized images and motion video into compact data streams that can be moved across networks with bandwidths too narrow to accommodate the uncompressed data. The operating program for the RISC microprocessor is stored in a volatile Instruction Random Access Memory (IRAM) in the form of firmware which can be downloaded at initialization.

Claims

1. A single chip digital video network apparatus, comprising on a single semiconductor substrate:

a physical layer circuit for interfacing to an asynchronous transfer mode (ATM) network;

an ATM cell interface circuit coupled to the physical layer circuit for receiving packets of data in an ATM network protocol format from the physical layer circuit;

a virtual channel RAM (VCR) coupled to the ATM cell interface circuit for storing packets of data;

a direct memory access-VCR (DMA-VCR) bus coupled to the VCR for transferring packets of data from the VCR;

a direct memory access (DMA) controller coupled to the DMA-VCR bus for controlling a transfer of packets of data from the VCR;

a random access memory for storing packets of data in an ATM network protocol format, the random access memory being coupled to the DMA controller;

an internal data bus coupled to the DMA controller for transferring packets of data from the DMA controller;

an ATM processing unit (APU) for converting data in the ATM network protocol format to an internal data format, said APU being coupled to the internal data bus;

a host data bus coupled to the DMA controller for transferring packets of data from the DMA controller;

a Motion Picture Experts Group (MPEG) data bus for transferring packets of data in an MPEG format;

a shared host RAM coupled to the host data bus and coupled to the MPEG data bus for storing data in the internal data format;

a video decoder coupled to the MPEG data bus for decoding MPEG full motion video data into a digital representation of a video signal; and

an audio decoder coupled to the MPEG data bus for decoding MPEG audio data into a digital representation of an audio signal.

2. The single chip digital video network apparatus according to claim 1, further comprising on said single semiconductor substrate:

a pacing rate unit (PRU) coupled to the internal data bus and coupled to the APU.

3. The single chip digital video network apparatus according to claim 2, further comprising on said single semiconductor substrate:

an instruction RAM (IRAM) coupled to the APU for storing instructions to be executed by the APU.

4. The single chip digital video network apparatus according to claim 3, further comprising:

random access memory (RAM) on said semiconductor substrate for storing frames of video during decoding operations, said RAM being coupled to said video decoder.

5. The single chip digital video network apparatus according to claim 4, further comprising:

a digital to analog converter circuit on said semiconductor substrate, the digital to analog converter circuit being coupled to said video decoder, the digital to analog converter circuit being operative to convert digital representations of a video signal to an analog video signal.

6. The single chip digital video network apparatus according to claim 1, further comprising:

a digital to analog converter circuit on said semiconductor substrate, the digital to analog converter circuit being coupled to said video decoder, the digital to analog converter circuit being operative to convert digital representations of a video signal to an analog video signal.