Method and apparatus for correlating a continuous phase modulated spread spectrum signal

• US 5,856,998 A
• Filed: 12/18/1996
• Issued: 01/05/1999
• Est. Priority Date: 09/09/1994
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Omnipoint Corp. (Deutsche Telekom AG)
• Inventors: Durrant, Randolph L., Burbach, Mark
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): GLUCK, JEFFREY WILLIAM
• Application Number:
  US08/769,187
• Time in Patent Office: 748 Days
• Field of Search: 375/200, 375/206, 375/208, 375/209, 375/210, 375/336, 375/343
• US Class Current: 375/150
• CPC Class Codes: H04B 1/707 using direct sequence modulation
• CPC Class Codes: H04B 1/708 Parallel implementation
• CPC Class Codes: H04B 1/7093 Matched filter type
• CPC Class Codes: H04B 2201/70701 featuring pilot assisted reception
• CPC Class Codes: H04J 13/10 Code generation
• CPC Class Codes: H04L 27/2014 in which the phase changes in a piecewise linear manner during each symbol period, e.g. minimum shift keying, fast frequency shift keying H04L27/201 takes precedence
• CPC Class Codes: H04L 27/2278 using correlation techniques, e.g. for spread spectrum signals
• CPC Class Codes: H04L 27/2332 using a non-coherent carrier

Abstract

A technique for modulating and demodulating continuous phase modulation (CPM) spread spectrum signals and variations thereof. A transmitter encodes M data bits using a selected spread spectrum code, divides the spread spectrum code into a plurality of chip codes (such as even chips and odd chips), independently modulates the even and odd chips with orthogonal carrier signals using CPM or a related technique, and superposes the plurality of resultants for transmission. A receiver receives the superposed spread spectrum signal, divides the spread spectrum signal into duplicate signals, separately demodulates the duplicate signals into an odd chip signal and an even chip signal, simultaneously attempts to correlate the odd chip signal with a locally generated odd chip sequence and the even chip signal with a locally generated even chip sequence, and interleaves the correlation signals into a unified correlation signal. The unified correlation signal may be compared against other correlation signals to determine the content of the transmitted data.

Claims

1. An apparatus for despreading a continuous phase modulated spread spectrum signal comprising:

a signal divider coupled to a received continuous phase modulated spread spectrum signal, said signal divider separating said spread spectrum signal into first and second duplicate signals, said spread spectrum signal generated by superposing a first transmitter signal derived from transitions between odd chips in a spreading code and a second transmitter signal derived from transitions between even chips in said spreading code, said odd chips comprising a plurality of odd preamble chips and a plurality of odd non-preamble chips, and said even chips comprising a plurality of even preamble chips and a plurality of even non-preamble chips,

a first demodulator coupled to said first signal and outputting a first demodulated signal,

a second demodulator coupled to said second signal and outputting a second demodulated signal,

a synchronization circuit, said synchronizing circuit comprising

a first parallel correlator connected to said first demodulated signal and said odd preamble chips, said first parallel correlator correlating odd chips of said first demodulated signal with said odd preamble chips and outputting a first correlation signal,

a second parallel correlator connected to said second demodulated signal and said odd preamble chips, said second parallel correlator correlating odd chips of said second demodulated signal with said odd preamble chips and outputting a second correlation signal,

a third parallel correlator connected to said second demodulated signal and said even preamble chips, said third parallel correlator correlating even chips of said second demodulated signal with said even preamble chips and outputting a third correlation signal,

a fourth parallel correlator connected to said first demodulated signal and an inverse of said even preamble chips, said fourth parallel correlator correlating even chips of said first demodulated signal with said inverse of said even preamble chips and outputting a fourth correlation signal,

a first adder having as inputs said first correlation signal and said third correlation signal, said first adder outputting a first intermediate preamble correlation signal,

a second adder having as inputs said second correlation signal and said fourth correlation signal, said second adder outputting a second intermediate preamble correlation signal,

a combining circuit having as inputs said first intermediate preamble correlation signal and said second intermediate correlation signal, said combining circuit outputting a unified preamble correlation signal,

a comparator having as inputs said unified preamble correlation signal and a threshold signal, said comparator outputting a serial correlation synchronization signal when said unified preamble correlation signal exceeds said threshold signal, and

a clock synchronizer connected to said serial correlation synchronization signal, said clock synchronizer outputting a serial correlator clock signal,

a first serial correlator circuit coupled to said first demodulated signal and to a locally generated signal representing said spreading code, said first serial correlator circuit clocked using said serial correlator clock signal and outputting a first odd correlation count and a first even correlation count, said first odd correlation count indicative of a level of correlation of said first demodulated signal with said odd non-preamble chips, and said first even correlation count indicative of a level of correlation of said first demodulated signal with an inverse of said even non-preamble chips,

a second serial correlator circuit coupled to said second sequence and to a locally generated signal representing said spreading code, said second serial correlator circuit clocked using said serial correlator clock signal and outputting a second odd correlation count and a second even correlation count, said second odd correlation count indicative of a level of correlation of said second demodulated signal with said odd non-preamble chips, and said second even correlation count indicative of a level of correlation of said second demodulated signal with said even non-preamble chips, and

a combiner coupled to said first odd correlation count, said second odd correlation count, said first even correlation count, and said second even correlation count, said combiner outputting a unified correlation signal.

2. The method of claim 1 wherein said step of demodulating said first signal comprises the step of generating a first local reference signal.

3. The method of claim 2 wherein said step of demodulating said second signal comprises the step of generating a second local reference signal 90-degrees phase offset from said first local reference signal.

4. The method of claim 1 further comprising the step of outputting a data symbol in response to a magnitude comparison of said unified correlation signal with at least one other correlation signal derived from matching said spread spectrum code to a different spread spectrum code.

5. An apparatus for despreading a continuous phase modulated spread spectrum signal comprising:

a signal divider coupled to a received continuous phase modulated spread spectrum signal, said signal divider separating said spread spectrum signal into first and second duplicate signals, said spread spectrum signal generated by superposing a first transmitter signal derived from transitions between odd chips in a spreading code and a second transmitter signal derived from transitions between even chips in said spreading code, said odd chips comprising a plurality of odd preamble chips and a plurality of odd non-preamble chips, and said even chips comprising a plurality of even preamble chips and a plurality of even non-preamble chips,

a first demodulator coupled to said first signal and outputting a first demodulated signal,

a second demodulator coupled to said second signal and outputting a second demodulated signal,

a synchronization circuit, said synchronizing circuit comprising

a first even/odd shift register having as an input said first demodulated signal and having a plurality of odd chip locations, said first even/odd shift register having outputs located at every odd chip location and at every even chip location,

a second even/odd shift register having as an input said second demodulated signal and having a plurality of odd chip locations, said second even/odd shift register having outputs located at every odd chip location and at every even chip location,

a first matched code filter having as inputs said outputs of every other odd chip location of said first even/odd shift register, for correlation with said odd preamble chips, said first matched code filter outputting a first correlation signal,

a second matched code filter having as inputs said outputs of every other odd chip location of said second even/odd shift register, for correlation with said odd preamble chips, said second matched code filter outputting a second correlation signal,

a third matched code filter having as inputs said outputs of every other even chip location of said second even/odd shift register, for correlation with said even preamble chips, said third matched code filter outputting a third correlation signal,

a fourth matched code filter having as inputs said outputs of every other even chip location of said first even/odd shift register, for correlation with said even preamble chips, said fourth matched code filter outputting a fourth correlation signal,

a first adder having as inputs said first correlation signal and said third correlation signal, said first adder outputting a first intermediate preamble correlation signal,

a second adder having as inputs said second correlation signal and said fourth correlation signal, said second adder outputting a second intermediate preamble correlation signal,

a combining circuit having as inputs said first intermediate preamble correlation signal and said second intermediate correlation signal, said combining circuit outputting a unified preamble correlation signal,

a comparator having as inputs said unified preamble correlation signal and a threshold signal, said comparator outputting a serial correlation synchronization signal when said unified preamble correlation signal exceeds said threshold signal, and

a clock synchronizer connected to said serial correlation synchronization signal, said clock synchronizer outputting a serial correlator clock signal,

a first serial correlator circuit coupled to said first demodulated signal and to a locally generated signal representing said spreading code, said first serial correlator circuit clocked using said serial correlator clock signal and outputting a first odd correlation count and a first even correlation count, said first odd correlation count indicative of a level of correlation of said first demodulated signal with said odd non-preamble chips, and said first even correlation count indicative of a level of correlation of said first demodulated signal with an inverse of said even non-preamble chips,

a second serial correlator circuit coupled to said second sequence and to a locally generated signal representing said spreading code, said second serial correlator circuit clocked using said serial correlator clock signal and outputting a second odd correlation count and a second even correlation count, said second odd correlation count indicative of a level of correlation of said second demodulated signal with said odd non-preamble chips, and said second even correlation count indicative of a level of correlation of said second demodulated signal with said even non-preamble chips, and

a combiner coupled to said first odd correlation count, said second odd correlation count, said first even correlation count, and said second even correlation count, said combiner outputting a unified correlation signal.

6. The apparatus of claim 5 wherein said first demodulator is coupled to a first local reference signal.

7. The apparatus of claim 6 wherein said second demodulator is coupled to a second local reference signal 90-degrees phase offset from said first local reference signal.

8. The apparatus of claim 5 further comprising a data generator coupled to said unified correlation signal and to a second correlation signal generated by a correlation between said spread spectrum signal and a different spread spectrum code, said data generator outputting a data symbol in response to a magnitude comparison between said unified correlation signal and said second correlation signal.