Programmable logic device for real time video processing

• US 5,857,109 A
• Filed: 04/11/1995
• Issued: 01/05/1999
• Est. Priority Date: 11/05/1992
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Giga Operations Corporation
• Inventors: Taylor, Brad
• Primary Examiner(s): Lim, Krisna
• Application Number:
  US08/419,835
• Time in Patent Office: 1,365 Days
• Field of Search: 395/800, 364/489
• US Class Current: 712/37
• CPC Class Codes: G09G 5/395 Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen G09G5/399 takes precedence

Abstract

A real time video processing system adds a programmable logic device between a conventional frame buffer and a conventional digital to analog converter to provide real time and off-screen processing power to enhance video output capabilities. The system may include a history FIFO connected to deliver the preceding line to the programmable logic device, allowing operations on a pixel in the current line, modified as needed by the status of one or more nearby pixels. The system may also include inputs for multiple video sources and may include input FIFOs for more random access to portions of the input stream. An alternative form of the system includes a crossbar switch and multiple memory devices, to allow switching among several possible frame buffer devices. One or more processing units can be added to manipulate a memory which is not the active frame buffer. The programmable logic device can be loaded with a configuration file stored in an associated memory or loaded from a host computer.

Claims

1. A real time video processing system comprising

a video input/output bus,

a crossbar switch connected to said video input/output bus,

a digital to analog converter (DAC) having a DAC input and a DAC output, the DAC input connected to said crossbar switch to receive a first or a second switchable, real time digital video signal and the DAC output providing a real time analog video signal,

a first frame buffer having a first input and a first output, said first input and said output being connected to said crossbar switch and connectable therethrough to said video input/output bus,

a second frame buffer having a second input and a second output, said second input and said output being connected to said crossbar switch and connectable therethrough to said video input/output bus,

a host computer input/output bus,

a first programmable logic device (PLD) having a first host input, a first switch input and a first PLD output,

said first host input connected to said host computer input/output bus and

said first switch input connected to said crossbar switch and connectable therethrough to said video input/output bus, said first frame buffer and said second frame buffer,

said first PLD output connected to said crossbar switch and connectable therethrough to said first frame buffer and said second frame buffer and to said DAC input to provide a first switchable, real time digital video signal to said DAC input,

a second programmable logic device (PLD) having a second host input, a second switch input and a second PLD output,

said second host input connected to said host computer input/output bus,

said second switch input connected to said crossbar switch and connectable therethrough to said video input/output bus, said first frame buffer and said second frame buffer,

said second PLD output connected to said crossbar switch and connectable therethrough to said first frame buffer and said second frame buffer and to said DAC input to provide a second switchable, real time digital video signal to said DAC input.

2. The real time video processing system of claim 1 further comprising a digital signal processing device connected to said first programmable logic device.

3. A real time video processing system comprising:

an input/output bus;

a frame buffer having a first input and a first output, said first input being connected to the input/output bus and said first output being connected to provide digital information;

a programmable logic device having a first input and an output, said first input of said programmable logic device being connected to said first output of said frame buffer and configured to process said digital information and to provide a real time video signal at said output of the programmable logic device;

a digital to analog converter having an input and an output, the input of which is connected to said output of said programmable logic device, wherein the output of said converter provides a real time analog video signal;

a second input for said programmable logic device;

a history FIFO having an input and an output, the input of which is connected to the output of said programmable logic device and the output of which is connected to said second input for said programmable logic device;

a second output from said frame buffer;

a third input to said programmable logic device connected to said second output from said frame buffer;

an input FIFO, having an input and an output, wherein said input FIFO is connected between said first output of said frame buffer and said first input of said programmable logic device;

a second input FIFO, having an input and an output, wherein said second input FIFO is connected between said second output of said frame buffer and said third input of said programmable logic device;

wherein said frame buffer has a second input which is connected to the output of said programmable logic device;

a memory device connected to said programmable logic device;

configuration data stored in said memory device, said configuration data suitable for describing and establishing a selected configuration to configure said programmable logic device; and

a means for loading said configuration data into said programmable logic device.

4. A real time video processing system comprising

a video input/output bus,

a video memory bus, digital information on said video memory bus,

a frame buffer comprising a frame buffer input connected to the video memory bus to retrieve digital information, and a frame buffer output connected to the video memory bus to provide digital information,

a video output module comprising a video bus input connected to said video input/output bus, a video memory output connected to said video memory bus, and a video memory input connected to said video memory bus,

a video processing unit connected to said video memory bus, said video processing unit comprising a programmable logic device having a PLD input and a PLD output, said PLD input connected to said video memory bus to receive digital information from said video memory bus and connected therethrough to said frame buffer output and to said video memory output, said PLD output connected to said video memory bus and connected therethrough to said frame buffer input and to said video memory input, said programmable logic device configured to process said digital information to provide a real time video signal at said output of the programmable logic device, and

said video output module further comprising a digital to analog converter having an input and an output, the input of which is connected to the video memory bus and connectible therethrough to said frame buffer output and to said PLD output, the output of said converter providing a real time analog video signal.

5. The real time video processing system of claim 4, said video processing unit further comprising a digital signal processing device connected to said programmable logic device.

6. The realtime video processing system of claim 4, said video processing unit further comprising a memory device connected to said programmable logic device and a digital signal processing device connected to said programmable logic device.

7. The real time video processing system of claim 4, said video processing unit further comprising a memory device connected to said programmable logic device, a digital signal processing device connected to said programmable logic device, and a zero delay buffer connected to said video memory bus between said bus and said programmable logic device.

8. The real time video processing system of claim 4 further comprising a host computer bus connected to said programmable logic device.

9. The real time video processing system of claim 4 further comprising a means for configuring said programmable logic device.