Multiprocessor system assigning system function to each processor in accordance with delay function and maintaining the system function assignment after the system is rebooted

• US 5,857,113 A
• Filed: 02/18/1997
• Issued: 01/05/1999
• Est. Priority Date: 06/10/1994
• Status: Expired due to Term

• Current Assignee: RPX Corporation
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Muegge, Shad William, Henderson, Paul, Stolp, Mark
• Primary Examiner(s): Luu, Le Hien
• Application Number:
  US08/802,431
• Time in Patent Office: 686 Days
• Field of Search: 370/228, 375/354, 395/182.11, 395/182.02, 395/676, 395/830, 395/829, 326/93
• US Class Current: 710/10
• CPC Class Codes: H04Q 11/0407 using a stored programme control

Abstract

An integrated network switch system which can uniquely and consistently detect and designate each processor on a bus without the relative position information, and allow a dynamic reallocation of the processors according to their designations. A pseudo code residing within each processor is implemented to effect the detecting and designating operation of the integrated network switch system. Additionally, a shared RAM and a hardware register which are made accessible to all processors on the bus at a fixed location are used to assist the designating operation of the system, and each processor'"'"'s memory is used to assist the delaying operation of the system. This assures that tasks among the processors are distributed according to their designations, and that each of the processors can be removed or added without any hard coded information.

Claims

1. A system with multiple processors, said system having a backplane for accommodating said multiple processors, no position being dedicated to a specific process and no processor being uniquely assigned a system function, said system comprising:

means for providing each processor with a different delay function, and

means for assigning each processor a different system function in accordance with the delay function provided the processor, and for maintaining the assigned system function to each processor after said system is rebooted.

2. The multiple processor system as claimed in claim 1, further comprising means for providing one of the system processors with no delay function, the absence of a delay function defining a system function to be carried out by that processor.

3. The multiple processor system as claimed in claim 1, wherein said system is an integrated network switching system.

4. A system with multiple processors, said system having a backplane for accommodating said multiple processors, no position being dedicated to a specific process and no processor being uniquely assigned a system function, said system comprising:

means for providing each processor with a different qualification identifier, and

means for assigning each processor a different system function in accordance with the qualification identifier provided the processor, and for maintaining the assigned system function to each processor after said system is rebooted.

5. The multiple processor system as claimed in claim 4, wherein said system is an integrated network switching system.

6. In a system with multiple processors, said system having a backplane for accommodating said multiple processors, no position being dedicated to a specific process and no processor being uniquely assigned a system function, a method for assigning system functions to the processors of said system comprising:

providing each processor with a different delay function,

assigning each processor a different system function in accordance with the delay function provided the processor, and

maintaining the assigned system function to each processor after said system is rebooted.

7. The method as claimed in claim 6, further comprising providing one of the system processors with no delay function, the absence of a delay function defining a system function to be carried out by that processor.

8. In a system with multiple processors, said system having a backplane for accommodating said multiple processors no position being dedicated to a specific process and no processor being uniquely assigned a system function, a method for associating each processor with a system function comprising:

providing each processor with a different qualification identifier,

assigning each processor a different system function in accordance with the qualification identifier provided the processor, and

maintaining the assigned system function to each processor after said system is rebooted.

9. An integrated network switch system with multiple processors, said system having a VME type common bus on a backplane for accommodating said multiple processors, no position being dedicated to a specific process and no processor being uniquely assigned a system function, said system comprising:

means for providing each processor with a different delay function, and

means for assigning each processor a different system function in accordance with the delay function provided the processorand for maintaining said assigned system function to each processor after said system is rebooted.

10. An integrated network switch system with multiple processors, said system having a VME type common bus on a backplane for accommodating said multiple processors, no position being dedicated to a specific process and no processor being uniquely assigned a system function, said system comprising:

means for providing each processor with a different qualification identifier without programming identification information into the processors, and

means for assigning each processor a different system function in accordance with the qualification identifier provided the processor and for maintaining said assigned system function to each processor after said system is rebooted.