Fabrication method for a thin film semiconductor device, the thin film semiconductor device itself, liquid crystal display, and electronic device

• US 5,858,819 A
• Filed: 02/15/1996
• Issued: 01/12/1999
• Est. Priority Date: 06/15/1994
• Status: Expired due to Term

• Current Assignee: Intellectual Keystone Technology LLC (Samsung Electronics Co. Ltd.)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Miyasaka, Mitsutoshi
• Primary Examiner(s): Niebling, John
• Assistant Examiner(s): LEBENTRITT, MICHAEL
• Application Number:
  US08/591,681
• Time in Patent Office: 1,062 Days
• Field of Search: 438/166, 438/486, 438/487, 438/149
• US Class Current: 438/149
• CPC Class Codes: F16C 2360/45 Turbo-molecular pumps
• CPC Class Codes: F16C 29/00 Bearings for parts moving only linearly F16C32/06 takes precedence; incorporated in flexible shafts F16C1/28 ; parts of bearings in general and special methods for making bearings or parts thereof in general F16C33/00
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: G02F 2202/104 poly-Si
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/02521 Materials
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02576 N-type
• CPC Class Codes: H01L 21/02579 P-type
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02661 In-situ cleaning
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 21/3105 After-treatment
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate

Abstract

In order to fabricate a high performance thin film semiconductor device using a low temperature process in which it is possible to use low price glass substrates, a thin film semiconductor device has been fabricated by forming a silicon film at less than 450° C., and, after crystallization, keeping the maximum processing temperature at or below 350° C.

In applying the present invention to the fabrication of an active matrix liquid crystal display, it is possible to both easily and reliably fabricate a large, high-quality liquid crystal display. Additionally, in applying the present invention to the fabrication of other electronic circuits as well, it is possible to both easily and reliably fabricate high-quality electronic circuits.

Claims

1. A fabrication process for fabricating a thin film semiconductor device using a low pressure chemical vapor deposition reactor, comprising:

forming an underlevel protection layer comprising an insulating material formed on at least a portion of a substrate; and

forming a silicon-containing semiconductor film on said underlevel protection layer, the silicon-containing semiconductor film being an active layer of a transistor, wherein the silicon-containing semiconductor film is formed with a low pressure chemical vapor deposition method using a higher silane as a source gas, the higher silane being Si_n H_2n+2, where n is an integer greater than or equal to 2,

wherein the higher silane has a flow rate per unit area R, with R≧

1.13×

10^-3 sccm/cm² when R=Q/A, wherein

A (cm²);

a total surface area inside the low pressure chemical vapor deposition reactor which can be covered with the silicon-containing semiconductor film, and

Q (sccm);

flow rate of the higher silane.

2. A fabrication process as described in claim 1, wherein the silicon-containing semiconductor film is formed with R≧

2.27×

10^-3 sccm/cm².

3. A fabrication process for fabricating a thin film semiconductor device having a semiconductor film formed on a surface of a glass substrate, said semiconductor film being an active layer of a transistor, the process comprising:

placing a plurality of substrate pairs in a hot wall, vertical low pressure chemical vapor deposition reactor, the substrate pairs being glass substrates and each one of the substrate pairs having a front side and a back side, a first one of the substrate pairs having a strain point higher than a strain point of a second one of the substrate pairs, the substrate pairs being placed in the vertical low pressure chemical vapor deposition reactor having the back sides of the first and second ones of the substrate pairs against each other, the first one of the substrate pairs being below the second one of the substrate pairs, and the first and second ones of the substrates pairs being approximately parallel to each other; and

forming the semiconductor film on the front sides of the first and second ones of the substrate pairs.

4. A fabrication process for fabricating a thin film semiconductor device having an underlevel protection layer formed on a portion of a substrate and a semiconductor film formed on said underlevel protection layer using a plasma enhanced chemical vapor deposition reactor, the underlevel protection layer comprising an insulating material and the semiconductor film being an active layer of a transistor, the process comprising:

exposing the underlevel protection layer to an oxygen plasma; and

then

forming the semiconductor film on top of said underlevel protection layer without breaking a vacuum of the plasma enhanced chemical vapor deposition reactor.

5. A fabrication process as described in claim 4, wherein the vacuum is engaged in the plasma enhanced chemical vapor deposition reactor between the exposing step and the forming step.

6. A fabrication process for fabricating a thin film semiconductor device having an underlevel protection layer formed on at least a portion of a substrate and a semiconductor film formed on said underlevel protection layer using a plasma enhanced chemical vapor deposition reactor, the underlevel protection layer comprising an insulating material and the semiconductor film being an active layer of a transistor, the process comprising:

exposing the underlevel protection layer to a hydrogen plasma; and

then

forming the semiconductor film on top of said underlevel protection layer without breaking a vacuum of the plasma enhanced chemical vapor deposition reactor.

7. A fabrication process for fabricating a thin film semiconductor device having an underlevel protection layer formed on at least a portion of a substrate and a semiconductor film formed on said underlevel protection layer using a plasma enhanced chemical vapor deposition reactor, the underlevel protection layer comprising an insulating material and the semiconductor film being an active layer of a transistor, the process comprising:

exposing the underlevel protection layer to an oxygen plasma;

then

exposing the underlevel protection layer to a hydrogen plasma without breaking a vacuum of the plasma enhanced chemical vapor deposition reactor; and

then

forming the semiconductor film on top of said underlevel protection layer.

8. A fabrication process as described in claim 7, wherein the vacuum is engaged in the plasma enhanced chemical vapor deposition reactor between the exposing the underlevel protection layer to the oxygen plasma step and the exposing the underlevel protection layer to the hydrogen plasma step.

9. A fabrication process for fabricating a thin film semiconductor device having an underlevel protection layer formed on at least a portion of a substrate and a semiconductor film formed on said underlevel protection layer using a plasma enhanced chemical vapor deposition reactor, the underlevel protection layer comprising an insulating material and the semiconductor film being an active layer of a transistor, the process comprising:

depositing the semiconductor film with a deposition rate of approximately 0.1 nm/s or more to form a mixed crystallinity semiconductor film; and

then

melt crystallizing said semiconductor film.

10. A fabrication process as described in claim 9, wherein the deposition rate is approximately 3.7 nm/s or more to form the mixed-crystallinity semiconductor film.

11. A fabrication process for fabricating a thin film semiconductor device having an underlevel protection layer formed on at least a portion of a substrate and a semiconductor film formed on said underlevel protection layer using a plasma enhanced chemical vapor deposition reactor, the underlevel protection layer comprising an insulating material and the semiconductor film being an active layer of a transistor, the process comprising:

forming a mixed-crystallinity semiconductor film, wherein chemical species containing constitutive elements of said semiconductor film and inert gases are used as source gases with a ratio of a flow rate of a gas containing the constitutive elements of the semiconductor film to a flow rate of the inert gases being less than about 1/33; and

melt crystallizing said mixed-crystallinity semiconductor film.

12. A fabrication process as described in claim 11, wherein the flow ratio is between about 1/124 and 1/40.67.