Geometrical control of device corner threshold

• US 5,858,866 A
• Filed: 11/22/1996
• Issued: 01/12/1999
• Est. Priority Date: 11/22/1996
• Status: Expired due to Fees

• Current Assignee: Qimonda AG (Infineon Technologies AG), International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Faul, Juergen, Berry, Wayne S., Haensch, Wilfried, Mohler, Rick L.
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US08/753,234
• Time in Patent Office: 781 Days
• Field of Search: 437/40 R, 437/41 R, 437/41 CS, 437/40 RG, 437/41 RG, 437/913, 437/52, 437/67, 148/DIG. 53, 438/299, 438/301, 438/306, 438/589, 438/424, 438/296
• US Class Current: 438/589
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: Y10S 977/888 Shaping or removal of materials, e.g. etching
• CPC Class Codes: Y10S 977/938 Field effect transistors, FETS, with nanowire- or nanotube-channel region

Abstract

Corner conduction in a conduction channel of a field effect transistor is controlled by the geometrical configuration of the gate oxide and gate electrode at the sides of the conduction channel. Rounding the corners of the conduction channel or forming depressions at edges of trench structures such as deep or shallow trench isolation structures and/or trench capacitors develop recesses in a surface of a substrate at an interface of active areas and trench structures in which a portion of the gate oxide and gate electrode are formed so that the gate oxide and gate electrode effectively wrap around a portion of the conduction channel of the transistor. Particularly when such transistors are formed in accordance with sub-micron design rules, the geometry of the gate electrode allows the electric field in the conduction channel to be modified without angled implantation to regulate the effects of corner conduction in the conduction channel. Thus the conduction characteristic near cut-off can be tailored to specific applications and conduction/cut-off threshold voltage can be reduced at will utilizing a simple, efficient and high-yield manufacturing process.

Claims

1. A method of manufacturing a semiconductor device including a field effect transistor, said method comprising the steps of:

forming a sacrificial oxide at a surface of an active area of a substrate and at an interface between said active area and a trench isolation structure having insulating material therein and a substantial planar surface, said active area being substantially a conduction channel;

over-etching said sacrificial oxide to form a depression in said insulating material of said isolation structure at a corner of said trench isolation structure; and

forming a gate oxide and a gate electrode over said conduction channel and in said depression,

said depression, said gate oxide and said gate electrode providing controlled threshold conduction characteristics in said conduction channel.

2. A method as recited in claim 1, wherein a portion of said sacrificial oxide is thermally grown.

3. A method as recited in claim 1, including the further step on implanting impurities in said active area of said substrate.