Method of making an inverse-T tungsten gate

• US 5,858,867 A
• Filed: 05/20/1996
• Issued: 01/12/1999
• Est. Priority Date: 05/20/1996
• Status: Expired due to Term

• Current Assignee: ProMOS Technologies, Inc.
• Original Assignee: Mosel Vitelic Incorporated
• Inventors: Hsia, Liang-Choo, Chang, Thomas Tong-Long
• Primary Examiner(s): Niebling, John
• Assistant Examiner(s): GURLEY, LYNNE ANN
• Application Number:
  US08/650,530
• Time in Patent Office: 967 Days
• Field of Search: 438/592, 438/655, 438/657, 438/682, 438/658, 438/664
• US Class Current: 438/592
• CPC Class Codes: H01L 21/28097 the final conductor layer next to the insulator being a metallic silicide
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A technique for fabricating an integrated circuit device 100 using an inverse-T tungsten gate structure 121 overlying a silicided layer 119 is provided. This technique uses steps of forming a high quality gate oxide layer 115 overlying a semiconductor substrate 111. The silicided layer 119 is defined overlying the gate oxide layer 115. The silicided layer 119 does not substantially react to this layer. The technique defines the inverse-T tungsten gate electrode layer 121 overlying the silicided layer 119. A top surface of this gate electrode may also be silicided 127 to further reduce the resistance of this device element.

Claims

1. A method of forming an integrated circuit device, said method comprising the steps of:

providing a partially completed semiconductor wafer, said partially completed semiconductor wafer comprising a gate insulating layer overlying a substrate; and

forming an inverse-T gate electrode structure, said inverse-T gate electrode structure comprising;

a silicided layer overlying said gate insulating layer; and

a gate electrode overlying said silicided layer, said silicided layer extending laterally from said gate electrode.

2. The method of claim 1 wherein said gate insulating layer is an oxide layer.

3. The method of claim 1 further comprising a step of forming lightly doped drain regions by implantation into said silicided layer.

4. The method of claim 3 further comprising a step of forming first sidewall spacers on said inverse-T gate electrode structure.

5. The method of claim 4 further comprising a step of annealing said lightly doped drain implant.

6. The method of claim 5 further comprising a step of removing said silicided layer extending outside said first sidewall spacers.

7. The method of claim 6 further comprising a step of removing said gate insulating layer overlying said lightly doped drain regions.

8. The method of claim 7 further comprising a step of forming second sidewall spacers adjacent to said first sidewall spacers.

9. The method of claim 8 further comprising a step of forming a silicided layer overlying a top region of said inverse-T gate electrode structure on a top region of said lightly doped drain regions.

10. The method of claim 9 further comprising a step of forming source/drain regions adjacent to said inverse-t gate electrode structure by implantation.

11. The method of claim 10 further comprising a step of annealing said source/drain regions.

12. The method of claim 1 wherein the gate electrode is made from a material selected from a group consisting of tungsten, titanium, and polysilicon.

13. The method of claim 1 wherein the silicided layer is formed using one of the group consisting of tungsten silicide, titanium silicide, platinum silicide, and cobalt silicide.

14. A method of forming an integrated circuit device comprising the steps of:

providing a partially completed semiconductor wafer, said partially completed semiconductor wafer comprising a gate insulating layer overlying a substrate;

forming a first silicided layer overlying said gate insulating layer;

forming a gate electrode overlying said silicided layer; and

etching said first silicided layer to form an etched silicided layer, wherein a portion of said etched silicided layer extends laterally from said gate electrode.

15. The method of claim 14 wherein the forming of the silicided layer step further comprises the steps of:

placing the partially completed semiconductor wafer in a chamber;

introducing dichlorosilene gas to the chamber; and

introducing tungsten hexaflouride to the chamber.

16. The method of claim 15 further comprising the step of heating the chamber to a temperature above 500 degrees Celsius.

17. The method of claims 14 further comprising the step of forming a first sidewall spacer adjacent said gate electrode and above said laterally extending portion of said etched silicided layer.

18. The method of claim 17 further comprising the step of forming a second sidewall spacer adjacent said first sidewall spacer.

19. The method of claim 14 further comprising the step of forming a second silicided layer above said gate electrode.

20. A method of forming an integrated circuit device comprising the steps of:

providing a partially completed semiconductor wafer, said partially completed semiconductor wafer comprising a gate insulating layer overlying a substrate;

forming a first silicided layer overlying said gate insulating layer;

forming a gate electrode overlying said silicided layer;

etching said first silicided layer to form an etched silicided layer, wherein a portion of said etched silicided layer extends laterally from said gate electrode;

forming a first sidewall spacer adjacent said gate electrode and at least partially above said etched silicided layer; and

forming a second sidewall spacer adjacent said first sidewall spacer.