Method for fabricating intermetal dielectric insulation using anisotropic plasma oxides and low dielectric constant polymers

• US 5,858,869 A
• Filed: 06/03/1997
• Issued: 01/12/1999
• Est. Priority Date: 06/03/1997
• Status: Expired due to Term

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Chen, Lai-Juh, Wang, Chien-Mei
• Primary Examiner(s): Chang, Joni
• Application Number:
  US08/868,343
• Time in Patent Office: 588 Days
• Field of Search: 438/597, 438/518, 438/622, 438/623, 438/624, 438/631, 438/633
• US Class Current: 438/597
• CPC Class Codes: H01L 21/02118 carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC polymers per se C08G, photoresist per se G03F
• CPC Class Codes: H01L 21/02131 the material being halogen doped silicon oxides, e.g. FSG
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/02282 liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
• CPC Class Codes: H01L 21/31612 on a silicon body
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76835 Combinations of two or more different dielectric layers having a low dielectric constant H01L21/76832 takes precedence
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for making multilevel electrical interconnections having a planar intermetal dielectric (IMD) with low dielectric constant k and good thermal conductivity was achieved. The method involves patterning an electrically conductive layer to form metal lines on which is deposited an anisotropic plasma oxide (APO) resulting in a thin oxide on the sidewalls of the metal lines and a much thicker oxide on top of the lines. A low dielectric constant (k) polymer is deposited and the polymer and APO are chem/mech polished back to the top of the metal lines. A fluorine-doped silicon oxide (FSG) is deposited, and via holes are etched to provide electrical connections for the next level of interconnections. The APO provides wider openings between metal lines filled with the low k dielectric polymer thereby reducing the RC time delay of the circuit. The thick top APO provides more processing latitude for polishing back the APO and low k polymer. The FSG provides a lower dielectric constant k for further reducing the RC delay and a better thermal conductivity constant K for minimizing the Joule heating when the circuit is powered up. The process can be repeated several times to form a planar multilevel interconnection for completing wiring on the integrated circuit.

Claims

1. A method for fabricating multilevel metal interconnections having low dielectric constant insulators on a substrate comprising the steps of:

a. providing a semiconductor substrate having semiconductor devices having contacts protected by a barrier layer;

b. depositing a first conductive layer for-contacting regions of said devices;

c. patterning said first conductive layer to form interconnections for said devices;

d. depositing an anisotropic plasma oxide over said patterned first conductive layer, said anisotropic plasma oxide being thicker on the top surface than on the sidewalls of said patterned conductive layer;

e. depositing a low dielectric constant insulator on said anisotropic plasma oxide;

f. planarizing said low dielectric constant insulator down to and further planarizing into said anisotropic plasma oxide by chemical/mechanical polishing to said top surface of said patterned first conductive layer;

g. depositing a fluorine-doped oxide on said low dielectric insulator on said patterned first conductive layer;

h. forming via holes in said fluorine-doped oxide to said patterned first conductive layer;

i. depositing a second conductive layer on said fluorine-doped oxide and in said via holes;

j. patterning said second conductive layer to form a second level of metal interconnections.

2. The method of claim 1, wherein said barrier layer is composed of titanium/titanium nitride and prevents aluminum from penetrating said devices having said contacts.

3. The method of claim 1, wherein said conductive layer is aluminum.

4. The method of claim 1, wherein said anisotropic plasma oxide is a silicon oxide deposited by plasma-enhanced chemical vapor deposition at a temperature of between about 375°

and 425°

C. using tetraethosiloxane (TEOS) and oxygen.

5. The method of claim 1, wherein said anisotropic plasma oxide is deposited to a thickness of between about 1000 and 5000 Angstroms on top surface of said patterned conductive layer, resulting in a respective thickness of said anisotropic oxide on the sidewalls of said patterned conductive layer of between about 170 and 850 Angstroms.

6. The method of claim 1, wherein said low dielectric constant insulating layer is an organic material having a dielectric constant of between about 1.9 and 3.7.

7. The method of claim 6, wherein said organic material is comprised of a polymer selected from a group consisting of polyimide, polysilsequioxane, benzocyclobutene (BCB), parylene N, fluorinated polyimide, parylene F, and amorphous Teflon.

8. The method of claim 1, wherein said low dielectric constant insulating layer is deposited to a thickness sufficient to fill the openings in said patterned conductive layer.

9. The method of claim 1, wherein said fluorine-doped oxide is a silicon oxide deposited by chemical vapor deposition to a thickness of between about 2000 and 10000 Angstroms.

10. The method of claim 1, wherein said fluorine-doped oxide has a fluorine concentration of between about 2 and 8 atomic percent and a dielectric constant of between about 3.8 and 3.1.

11. A method for fabricating multilevel metal interconnections having low dielectric constant insulators on a substrate comprising the steps of:

a. providing a semiconductor substrate having semiconductor devices having contacts protected by a barrier layer;

b. depositing a conductive layer for contacting regions of said devices;

c. patterning said conductive layer to form interconnections for said devices;

d. depositing an anisotropic plasma oxide over said patterned conductive layer, said anisotropic plasma oxide being thicker on the top surface than on the sidewalls of said patterned conductive layer;

e. depositing a low dielectric constant insulator on said anisotropic plasma oxide;

f. planarizing said low dielectric constant insulator down to and further planarizing into said anisotropic plasma oxide by chemical/mechanical polishing to said top surface of said patterned conductive layer;

g. depositing a fluorine-doped oxide on said low dielectric insulator on said patterned conductive layer;

h. forming via holes in said fluorine-doped oxide to said patterned conductive layer;

i. performing elements b. through h. n times, where n is the number of said patterned conductive layers required to complete said multilevel metal interconnections on an integrated circuit.

12. The method of claim 11, wherein said barrier layer is composed of titanium/titanium nitride and prevents aluminum from penetrating said devices having said contacts.

13. The method of claim 11, wherein said conductive layer is aluminum.

14. The method of claim 11, wherein said anisotropic plasma oxide is a silicon oxide deposited by plasma enhanced chemical vapor deposition at a temperature of between about 375°

and 425°

C. using tetraethosiloxane (TEOS) and oxygen.

15. The method of claim 11, wherein said anisotropic plasma oxide is deposited to a thickness of between about 1000 and 5000 Angstroms on top surface of said patterned conductive layer, resulting in a respective thickness of said anisotropic oxide on the sidewalls of said patterned conductive layer of between about 170 and 850 Angstroms.

16. The method of claim 11, wherein said low dielectric constant insulating layer is an organic material having a dielectric constant of between about 1.9 and 3.7.

17. The method of claim 16, wherein said organic material is comprised of a polymer selected from a group consisting of polyimide, polysilsequioxane, benzocyclobutene (BCB), parylene N, fluorinated polyimide, parylene F, and amorphous Teflon.

18. The method of claim 11, wherein said low dielectric constant insulating layer is deposited to a thickness sufficient to fill the openings in said patterned conductive layer.

19. The method of claim 11, wherein said fluorine-doped oxide is a silicon oxide deposited by chemical vapor deposition to a thickness of between about 2000 and 10000 Angstroms.

20. The method of claim 11, wherein said fluorine-doped oxide has a fluorine concentration of between about 2 and 8 atomic percent and a dielectric constant of between about 3.8 and 3.1.