Semiconductor device
First Claim
1. An insulated gate field effect transistor formed on an insulating surface, having at least a channel region, a gate insulating layer in contact with said channel region and a gate electrode insulated from said channel region by said gate insulating layer, said channel region comprising a semiconductor material having crystallinity,wherein said semiconductor material comprises silicon doped with hydrogen and a quadrivalent element, and a concentration of said quadrivalent element is not higher than 10 mol %.
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Abstract
A semiconductor device which has a non-single crystal semiconductor layer formed on a substrate and in which the non-single crystal semiconductor layer is composed of a first semiconductor region formed primarily of non-single crystal semiconductor and a second semi-conductor region formed primarily of semi-amorphous semiconductor. The second semi-conductor region has a higher degree of conductivity than the first semiconductor region so that a semi-conductor element may be formed.
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Citations
30 Claims
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1. An insulated gate field effect transistor formed on an insulating surface, having at least a channel region, a gate insulating layer in contact with said channel region and a gate electrode insulated from said channel region by said gate insulating layer, said channel region comprising a semiconductor material having crystallinity,
wherein said semiconductor material comprises silicon doped with hydrogen and a quadrivalent element, and a concentration of said quadrivalent element is not higher than 10 mol %.
- 4. An insulated gate field effect transistor formed on an insulating surface, having at least a channel region, a gate insulating layer in contact with said channel region and a gate electrode insulated from said channel region by said gate insulating layer, said channel region comprising a non-single crystalline semiconductor material comprising (a) a semiconductor selected from the group consisting of silicon, germanium and a combination thereof, (b) a recombination center neutralizer containing hydrogen, and (c) a quadrivalent element selected from the group consisting of Sn and Pb wherein said semiconductor material has crystallinity and a concentration of said recombination center neutralizer is not higher than 5 mol %, and a concentration of said quadrivalent element is not higher than 10 mol %.
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7. An insulated gate field effect transistor formed on an insulating surface, having at least a channel region, a gate insulating layer in contact with said channel region and a gate electrode insulated from said gate insulating layer, said channel region comprising a semiconductor material having crystallinity,
wherein said semiconductor material comprises silicon and germanium doped with a recombination center neutralizer selected from the group consisting of hydrogen and fluorine, and a concentration of said germanium is not higher than 10 mol %.
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20. An insulated gate field effect transistor comprising:
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a semiconductor layer comprising silicon having crystallinity formed on an insulating surface; source and drain regions formed within said semiconductor layer, said source and drain regions having one of N type or P type conductivity; a channel region formed within said semiconductor layer between said source and drain regions, said channel region doped with a dopant impurity having a conductivity type opposite to the conductivity type of said source and drain regions; a gate insulating film adjacent to said channel region; and a gate electrode adjacent to said gate insulating film, wherein said semiconductor layer is doped with a dangling bond neutralizer and a quadrivalent element, and a concentration of said quadrivalent element is not higher than 10 mol %. - View Dependent Claims (21, 22, 23, 28)
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24. An insulated gate field effect transistor comprising:
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a semiconductor layer comprising silicon and germanium having crystallinity formed on an insulating surface; source and drain regions formed within said semiconductor layer, said source and drain regions having one of N type or P type conductivity; a channel region formed within said semiconductor layer between said source and drain regions, said channel region doped with a dopant impurity having a conductivity type opposite to the conductivity type of said source and drain regions; a gate insulating film adjacent to said channel region; and a gate electrode adjacent to said gate insulating film, wherein said semiconductor layer is doped with a dangling bond neutralizer, and a concentration of said germanium is not higher than 10 mol %. - View Dependent Claims (25, 29)
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Specification