Semiconductor device

• US 5,859,444 A
• Filed: 02/05/1997
• Issued: 01/12/1999
• Est. Priority Date: 08/08/1991
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Okada, Teruhiko, Kuriyama, Hirotada, Kohno, Yoshio
• Primary Examiner(s): MEIER, STEPHEN D
• Application Number:
  US08/795,207
• Time in Patent Office: 706 Days
• Field of Search: 257/66, 257/67, 257/347
• US Class Current: 257/66
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78636 with supplementary region or layer for improving the flatness of the device
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]

Abstract

A semiconductor device is an SRAM cell having a pair of access transistors, a pair of driver transistors and a pair of load transistors. A gate electrode of the load transistor is electrically connected to a region of a semiconductor substrate which is surrounded by a gate electrode of the driver transistor, a channel region of the load transistor is formed opposite to the gate electrode of the load transistor with an insulating film therebetween, and a pair of source/drain regions of the load transistor are formed to sandwich the channel region.

Claims

1. A semiconductor device including an SRAM cell having a pair of access transistors, a pair of driver transistors and a pair of load transistors on a semiconductor substrate, comprising:

a first impurity region formed at a region of said semiconductor substrate sandwiched between a gate electrode of one of said pair of access transistor and a gate electrode of one of said pair of driver transistors;

a second impurity region formed at a region of said semiconductor substrate sandwiched between a gate electrode of another access transistor and a gate electrode of another driver transistor, without a gate electrode of a driver transistor between said second impurity region and said gate electrode of another access transistor;

a gate electrode of one of said load transistors connected to said second impurity region;

a channel region of said one of the load transistors formed across the gate electrode of said one of the load transistors with an insulating film therebetween; and

a pair of source/drain regions of said one of the load transistors formed to sandwich said channel region, wherein

one of the pair of source/drain regions of said one of the load transistors is connected to said first impurity region; and

the channel region of the load transistor and a first impurity region connected to one of the pair of source/drain regions are provided shifted from each other.

2. The semiconductor device according to claim 1, wherein

said access transistors and said driver transistors are bulk transistors, and

said one of the load transistors is a thin film transistor.

3. The semiconductor device of claim 1, wherein the channel region of said one of the load transistors is provided between the gate electrode of one of said pair of driver transistors and the gate electrode of one of said pair of access transistors.

4. The semiconductor device according to claim 1, wherein the gate electrodes of the access and driver transistors extend parallel to one another.

5. The semiconductor device according to claim 1, wherein the channel region of said one of the load transistors extends between the gate electrode of said another access transistor and said gate electrode of said another driver transistor.

6. The semiconductor device according to claim 1, wherein the gate electrode of said one of said load transistors is between the second impurity region and the channel region of said one of said load transistors.

7. The semiconductor device of claim 1, wherein a channel region of a load transistor extends between a gate electrode of an access transistor and a gate electrode of a driver transistor.

8. The semiconductor device according to claim 1, wherein the channel region of the load transistor is two-dimensionally linear.

9. A semiconductor device, comprising:

a semiconductor substrate;

a gate electrode of a first access transistor and a gate electrode of a first driver transistor as well as a gate electrode of a second access transistor and a gate electrode of a second driver transistor formed at a prescribed distance away from each other on a main surface of said semiconductor substrate with a gate oxide film therebetween;

a first impurity region formed at the main surface of said semiconductor substrate to be sandwiched between the gate electrode of said first access transistor and the gate electrode of said first driver transistor;

a second impurity region formed at the main surface of said semiconductor substrate to be sandwiched between the gate electrode of said second access transistor and the gate electrode of said second driver transistor, without a gate electrode of a driver transistor between said second impurity region and said gate electrode of said second access transistor;

a first conductive layer electrically connected to said first impurity region and formed above the gate electrode of said first access transistor and the gate electrode of said first driver transistor with a first interlayer insulating film therebetween;

a gate electrode of a load transistor formed above said second impurity region with said first interlayer insulating film therebetween to extend over the gate electrode of said second access transistor and the gate electrode of said second driver transistor; and

a second conductive layer formed above the gate electrode of said load transistor with a second interlayer insulating film therebetween, having a channel region of the load transistor formed across the gate electrode of said load transistor and a pair of impurity regions of the load transistor formed to sandwich the channel region, and having one of the pair of impurity regions of said load transistor electrically connected to said first conductive layer, wherein the channel region of the load transistor and a first impurity region connected to one of the pair of source/drain regions are provided shifted from each other.

10. The semiconductor device according to claim 9, wherein

said first and second access transistors as well as said first and second driver transistors are bulk transistors, and

said load transistor is a thin film transistor.

11. The semiconductor device of claim 9, wherein the channel region of said load transistor is provided between the gate electrode of said second driver transistor and the gate electrode of said second access transistor.

12. The semiconductor device according to claim 9, wherein the channel region of the load transistor is two-dimensionally linear.

13. A semiconductor device, comprising:

a semiconductor substrate;

a gate electrode of a first access transistor and a gate electrode of a first driver transistor as well as a gate electrode of a second access transistor and a gate electrode of a second driver transistor formed at a prescribed distance away from each other on a main surface of said semiconductor substrate with a gate oxide film therebetween;

a first impurity region formed at the main surface of said semiconductor substrate to be sandwiched between the gate electrode of said first access transistor and the gate electrode of said first driver transistor;

a second impurity region formed at the main surface of said semiconductor substrate to be sandwiched between the gate electrode of said second access transistor and the gate electrode of said second driver transistor, without a gate electrode of a driver transistor between said second impurity region and said gate electrode of said second access transistor;

a first conductive layer electrically connected to said first impurity region and formed above the gate electrode of said first access transistor and the gate electrode of said first driver transistor with a first interlayer insulating film therebetween;

a gate electrode of a load transistor formed above said second impurity region with said first interlayer insulating film therebetween to extend above the gate electrode of said second access transistor and the gate electrode of said second driver transistor; and

a second conductive layer formed above the gate electrode of said load transistor with a second interlayer insulating film therebetween, having a channel region of the load transistor formed across the gate electrode of said load transistor and a pair of impurity regions of the load transistor formed to sandwich the channel region, wherein the channel region of the load transistor and a first impurity region connected to one of the pair of source/drain regions are provided shifted from each other.

14. The semiconductor device according to claim 13, wherein the channel region of the load transistor is two-dimensionally linear.