Multiple transistor integrated circuit with thick copper interconnect
First Claim
1. A multiple transistor integrated circuit with a thick metal interconnect structure;
- comprising;
a plurality of gate bond pads, each for receiving a gate input to a respective LDMOS transistor;
a plurality of source bond pads, each for receiving a source input to a respective LDMOS transistor, all coupled together and to a common source buss;
a plurality of columns of multiple rows of diffusion regions, said diffusion regions alternating and being of a first and a second conductivity type;
first level metal layers fabricated over and electrically contacting each of said diffusion regions, said first level metal layers forming source stripes and drain stripes;
a plurality of columnar second level metal source busses, each coupled to said common source buss and each partially overlying a respective one of said plurality of columns of multiple rows of diffusions, each columnar second level metal source buss being coupled to selected ones of said source stripes;
a plurality of columnar second level metal drain busses, each coupled to a respective one of said drain bond pads, each partially overlying a respective one of said plurality of columns of multiple rows of diffusions and each being spaced apart from said plurality of columnar second level metal source busses, said source and drain busses being alternating columnar busses;
a plurality of third level thick metal source shorting busses comprised of a metal having a greater conductivity than the metals of said first level metal layers and second level metal source busses, each associated with and partially overlying a respective one of said source busses; and
a plurality of third level thick metal drain shorting busses comprised of a metal having a conductivity that is greater than the conductivity of said first level metal layers and second level drain busses, each associated with and partially overlying a respective one of said drain busses;
the third level thick metal source and drain shorting busses being in electrical contact with said source and drain busses and lowering the on resistance of the LDMOS transistors on the integrated circuit.
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Accused Products
Abstract
An interconnection structure and method for a multiple transistor integrated circuit power device is disclosed. A power integrated circuit is formed of a plurality of source and drain diffusion regions to be coupled together to form the source and drain of multiple LDMOS transistors. Each diffusion region has a first metal layer stripe formed over it and in electrical contact with it. A second metal layer conductor is formed over a plurality of the first metal layer stripes, and selectively contacts the first metal layer stripes to form source and drain busses. Polysilicon gate busses are provided as well. A thick third metal layer is then formed over each second metal layer bus, either physically contacting it or selectively electrically contacting it. The thick third level metal is fabricated of a highly conductive material, such as copper. The resulting on resistance for the transistors on the integrated circuit is substantially reduced by the use of the thick third metal layer. Current debiasing and electromigration problems of the prior art are reduced or eliminated. A seven transistor integrated circuit formed from power transistors and incorporating the invention is described. Other devices, systems and methods are also disclosed.
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Citations
18 Claims
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1. A multiple transistor integrated circuit with a thick metal interconnect structure;
- comprising;
a plurality of gate bond pads, each for receiving a gate input to a respective LDMOS transistor; a plurality of source bond pads, each for receiving a source input to a respective LDMOS transistor, all coupled together and to a common source buss; a plurality of columns of multiple rows of diffusion regions, said diffusion regions alternating and being of a first and a second conductivity type; first level metal layers fabricated over and electrically contacting each of said diffusion regions, said first level metal layers forming source stripes and drain stripes; a plurality of columnar second level metal source busses, each coupled to said common source buss and each partially overlying a respective one of said plurality of columns of multiple rows of diffusions, each columnar second level metal source buss being coupled to selected ones of said source stripes; a plurality of columnar second level metal drain busses, each coupled to a respective one of said drain bond pads, each partially overlying a respective one of said plurality of columns of multiple rows of diffusions and each being spaced apart from said plurality of columnar second level metal source busses, said source and drain busses being alternating columnar busses; a plurality of third level thick metal source shorting busses comprised of a metal having a greater conductivity than the metals of said first level metal layers and second level metal source busses, each associated with and partially overlying a respective one of said source busses; and a plurality of third level thick metal drain shorting busses comprised of a metal having a conductivity that is greater than the conductivity of said first level metal layers and second level drain busses, each associated with and partially overlying a respective one of said drain busses; the third level thick metal source and drain shorting busses being in electrical contact with said source and drain busses and lowering the on resistance of the LDMOS transistors on the integrated circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
- comprising;
Specification