Programming architecture for a programmable integrated circuit employing antifuses

• US 5,859,543 A
• Filed: 09/17/1997
• Issued: 01/12/1999
• Est. Priority Date: 06/21/1996
• Status: Expired due to Term

• Current Assignee: QuickLogic Corporation
• Original Assignee: QuickLogic Corporation
• Inventors: Kolze, Paige A.
• Primary Examiner(s): Santamauro, Jon
• Assistant Examiner(s): LE, DON P
• Application Number:
  US08/931,895
• Time in Patent Office: 482 Days
• Field of Search: 326/38-41
• US Class Current: 326/41
• CPC Class Codes: H03K 17/223 in field-effect transistor switches
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17764 for reliability
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A programmable integrated circuit such as a field programmable gate array (see FIG. 3) has a few long routing wire segments for transmitting signals long distances across the integrated circuit. These long routing wire segments can be coupled together with programmed antifuses. A high-drive output driver may be used to drive signals a long distance through such coupled together long routing wire segments giving rise to large switching currents across the programmed antifuses that couple the long wire segments together. In some types of antifuses, programmed antifuse reliability is dependent upon maintaining the programming current used to program the antifuse a certain factor greater than the peak switching current flowing through the antifuse during normal operation. The antifuses in these long wire segments therefore should be programmed with proportionately larger programming currents. To increase the programming currents with which these antifuses are programmed, programming current is supplied onto each of the long routing segments from two different programming conductors via two different programming transistors.

Claims

1. A programmable integrated circuit, comprising:

a plurality of logic modules aligned in a row extending in a first dimension, a distance A existing between two adjacent ones of the logic modules;

a first programming conductor extending in a second dimension from a first programming driver, the second dimension being perpendicular to the first dimension;

a second programming conductor extending in the second dimension from a second programming driver;

a first wire segment extending a distance more than two times as long as distance A in the first dimension to a connection node;

a first programming transistor having a first electrode coupled to the connection node and having a second electrode coupled to the first programming conductor;

a second programming transistor having a first electrode coupled to the connection node and having a second electrode coupled to the second programming conductor;

a programming control conductor being coupled to a gate electrode of the first programming transistor and to a gate electrode of the second programming transistor;

a plurality of second wire segments extending parallel to one another in the second dimension, each of the second wire segments crossing the first wire segment; and

a plurality of antifuses, one of the antifuses being disposed at each location where a second wire segment crosses the first wire segment.

2. The programmable integrated circuit of claim 1, wherein the programming control conductor has a first portion which extends in the second dimension and couples to the gates of the first and second programming transistors, and wherein the programming control conductor also has a second portion which extends in the first dimension a distance greater than two times distance A.

3. The programmable integrated circuit of claim 1, further comprising:

a third wire segment extending a distance more than two times as long as distance A in the first dimension to a second connection node, the third wire segment being substantially collinear with respect to the first wire segment;

an interconnect antifuse which if programmed couples the first wire segment to the third wire segment,

a third programming conductor extending in the second dimension from a third programming driver;

a fourth programming conductor extending in the second dimension from a fourth programming driver;

a third programming transistor having a first electrode coupled to the second connection node and having a second electrode coupled to the third programming conductor; and

a fourth programming transistor having a first electrode coupled to the second connection node and having a second electrode coupled to the fourth programming conductor, the third programming transistor having a gate electrode that is coupled to a gate electrode of the fourth programming transistor.

4. The programmable integrated circuit of claim 3, the first and second programming drivers being disposed one side of the first and third wire segments and the third and fourth programming drivers being disposed on another side opposite the one side.