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Charge recycling differential logic (CRDL) circuit and devices using the same

  • US 5,859,548 A
  • Filed: 07/31/1996
  • Issued: 01/12/1999
  • Est. Priority Date: 07/24/1996
  • Status: Expired due to Term
First Claim
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1. A logic circuit operating under a clock signal of first and second levels, comprising:

  • first and second nodes;

    means for pulling-up said first node to a first potential when the clock signal transits from the first level to said second level;

    means for pulling-down said second node to a second potential when the clock signal transits from the first level to the second level; and

    means for equalizing said first and second nodes to a third potential between said first and second potentials when the clock signal transits from the second level to the first level.

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