Charge recycling differential logic (CRDL) circuit and devices using the same

• US 5,859,548 A
• Filed: 07/31/1996
• Issued: 01/12/1999
• Est. Priority Date: 07/24/1996
• Status: Expired due to Term

• Current Assignee: LG Semicon Co Ltd (SK Hynix Inc.)
• Original Assignee: LG Semicon Co Ltd (SK Hynix Inc.)
• Inventors: Kong, Bai-Sun
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Ho, Hoai V.
• Application Number:
  US08/688,881
• Time in Patent Office: 895 Days
• Field of Search: 326/95, 326/98, 326/113, 365/205, 365/207
• US Class Current: 326/113
• CPC Class Codes: G06F 2207/3872 Precharge of output to prevent leakage
• CPC Class Codes: G06F 2207/3884 Pipelining
• CPC Class Codes: G06F 7/501 Half or full adders, i.e. basic adder cells for one denomination
• CPC Class Codes: G06F 7/503 using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal
• CPC Class Codes: G06F 7/505 in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
• CPC Class Codes: G06F 7/507 using selection between two conditionally calculated carry or sum values
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: H03K 19/0019 by energy recovery or adiabatic operation
• CPC Class Codes: H03K 19/0963 using transistors of complementary type H03K19/0966 takes precedence
• CPC Class Codes: H03K 19/1738 using cascode switch logic [CSL] or cascode emitter coupled logic [CECL]
• CPC Class Codes: H03K 19/215 using field-effect transistors
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors

Abstract

A novel logic family, called Charge Recycling Differential Logic (CRDL) circuit, reduces power consumption by utilizing a charge recycling technique and has a speed comparable to those of conventional dynamic logic circuits. The CRDL circuit also has improved noise margin due to inherently static operation. An 8-bit Manchester carry chains and full adders were fabricated using a 0.8 μm single-poly double-metal n-well CMOS technology. The measurement results indicate about 16-48% improvements in power-delay product are obtained compared with Differential Cascode Voltage Switch (DCVS) circuit.

Claims

1. A logic circuit operating under a clock signal of first and second levels, comprising:

first and second nodes;

means for pulling-up said first node to a first potential when the clock signal transits from the first level to said second level;

means for pulling-down said second node to a second potential when the clock signal transits from the first level to the second level; and

means for equalizing said first and second nodes to a third potential between said first and second potentials when the clock signal transits from the second level to the first level.

2. The logic circuit of claim 1, wherein said pulling-up means comprises a pair of cross-coupled transistors.

3. The logic circuit of claim 2, wherein said pair of cross-coupled transistor comprises:

a first transistor having a control electrode and first and second electrodes;

a second transistor having a control electrode and first and second electrodes, wherein

said first electrodes of said first and second transistors receive a first predetermined source potential, said control electrode of said first transistor being coupled to said equalizing means and said second node, and said control electrode of said second transistor is coupled to said equalizing means and said first node.

4. The logic circuit of claim 3, wherein said equalizing means is a third transistor having a control electrode and first and second electrodes, said control electrode receiving the clock signal and said first and second electrodes coupled to said first and second transistors, respectively.

5. The logic circuit of claim 4, wherein said third transistor is an nMOS transistor.

6. The logic circuit of claim 3, wherein each of said first and second transistors has a threshold voltage higher than said third potential.

7. The logic circuit of claim 6, wherein said first and second transistors are pMOS transistors.

8. The logic circuit of claim 1, wherein said pull-down means is a passive transistor logic network for implementing a predetermined logic function.

9. The logic circuit of claim 1, wherein said pull-down means is a cascode logic network for implementing a predetermined logic function.

10. The logic circuit of claim 1, further comprising at least one of

a sense amplifier to accelerate a potential pull-down transition of said first and second nodes;

and

means for generating an output signal.

11. The logic circuit of claim 10, wherein at least one of said sense amplifier and said generating means comprise fourth, fifth and sixth transistors, said fourth transistor being coupled to said first and second nodes, said fifth transistor being coupled to said first and second nodes, and said sixth transistor being coupled to said fourth and fifth transistors and receiving one of an enable signal and the clock signal.

12. The logic circuit of claim 11, wherein first and control electrodes of said fourth transistor are coupled to said first and second nodes, respectively, first and control electrodes of said fifth transistor are coupled said second and first nodes, respectively, and second electrodes of said fourth and fifth transistors are commonly coupled to a first electrode of said sixth transistor.

13. The logic circuit of claim 12, wherein a control electrode of said sixth transistor receives one of the enable signal and the clock signal and a second electrode of said sixth transistor is coupled to a predetermined second potential.

14. The logic circuit of claim 13, wherein said fourth, fifth and sixth transistors are nMOS transistors.

15. The logic circuit of claim 13, wherein said fourth and fifth transistors are pMOS transistors and said sixth transistor is an nMOS transistor.

16. The logic circuit of claim 1, wherein said third potential is about one half of a potential difference between said first and second potentials.

17. The logic circuit of claim 1, further comprising means for providing a potential swing between said first and second potentials in response to a potential swing from said third potential to one of said first and second potential.

18. A logic circuit comprising:

first and second nodes;

a pair of cross-coupled first and second transistors coupled to said first and second output nodes;

a third transistor coupled to said first and second transistors, said third transistor equalizing said first and second nodes to potentials which are about equal to one another; and

a logic network coupled to said first and second nodes for implementing a predetermined logic function, wherein each of said first, second and third transistors includes a first electrode, a second electrode and a control electrode, said control electrodes of said first and second transistors coupled to said first and second electrodes, respectively, of said third transistor and said control electrodes of said first and second transistors coupled to said second and first nodes, respectively, and second electrodes of said first and second transistors coupled to said first and second nodes, respectively, and the first electrode of said first and second transistors coupled for receiving a first predetermined source potential.

19. The logic circuit of claim 18, wherein said logic network is an nMOS passive transistor logic network.

20. The logic circuit of claim 18, wherein said logic network is an nMOS cascode logic network.

21. The logic circuit of claim 18, wherein each of said first and second transistors has a threshold voltage higher than said said potential of said first and second nodes which has been equalized by said third transistor.

22. The logic circuit of claim 18, wherein said third transistor is coupled for receiving a clock signal, said first transistor outputting a first potential at the first output node when said clock signal transits from a first level to a second level, said second transistor outputting a second potential at said second output node when said clock signal transits from the first level to the second level, and said third transistor equalizing said first and second output nodes to a third potential, which is between said first and second potentials, when the clock signal transits from the second level to the first level.

23. A method for recycling charges stored in first and second parasitic capacitors of first and second nodes, repectively, comprising the steps of:

pulling-up the first node to a first potential when a clock signal transits from a first level to a second level;

pulling-down the second node to a second potential when the clock signal transits from the first level to the second level; and

equalizing the first and second nodes to a third potential between said first and second potentials when the clock signal transits from the second level to the first level.

24. The method of claim 23 further comprising at least one of the steps of:

accelerating a potential pull-down transition of said first and second output nodes; and

generating an output signal.

25. A logic circuit comprising:

first and second nodes;

a pair of cross-coupled first and second transistors coupled to said first and second output nodes;

a third transistor coupled to said first and second transistors, said third transistor equalizing said first and second nodes to potentials which are about equal to one another;

a logic network coupled to said first and second nodes for implementing a predetermined logic function; and

at least one of a sense amplifier to accelerate a potential pull-down transition of said first and second nodes, and means for generating an output signal.

26. The logic circuit of claim 25, wherein at least one of said sense amplifier and said generating means comprise fourth, fifth and sixth transistors, said fourth transistor being coupled to said first and second nodes, said fifth transistor being coupled to said first and second nodes, and said sixth transistor being coupled to said fourth and fifth transistors and receiving one of an enable signal and an clock signal.

27. The logic circuit of claim 26, wherein first and control electrodes of said fourth transistor are coupled to said first and second nodes, respectively, first and control electrodes of said fifth transistor are coupled said second and first nodes, respectively, and second electrodes of said fourth and fifth transistors are commonly coupled to a first electrode of said sixth transistor.

28. The logic circuit of claim 27, wherein a control electrode of said sixth transistor receives one of the enable signal and the clock signal and a second electrode of said sixth transistor is coupled to a predetermined second potential.

29. The logic circuit of claim 28, wherein said fourth, fifth and sixth transistors are nMOS transistors.

30. The logic circuit of claim 28, wherein said fourth and fifth transistors are pMOS transistors and said sixth transistor is an nMOS transistor.

31. The logic circuit of claim 25, wherein said third transistor is coupled for receiving a clock signal, said first transistor outputting a first potential at the first output node when said clock signal transits from a first level to a second level, said second transistor outputting a second potential at said second output node when said clock signal transits from the first level to the second level, and said third transistor equalizing said first and second output nodes to a third potential, which is between said first and second potentials, when the clock signal transits from the second level to the first level.

32. A logic circuit comprising:

first and second nodes;

a pair of cross-coupled first and second transistors coupled to said first and second output nodes;

a third transistor coupled to said first and second transistors, said third transistor equalizing said first and second nodes to potentials which are about equal to one another; and

a logic network coupled to said first and second nodes for implementing a predetermined logic function, wherein said first and second transistors are pMOS transistors, and said third transistor is an nMOS transistor.

33. The logic circuit of claim 32, wherein said third transistor is coupled for receiving a clock signal, said first transistor outputting a first potential at the first output node when said clock signal transits from a first level to a second level, said second transistor outputting a second potential at said second output node when said clock signal transits from the first level to the second level, and said third transistor equalizing said first and second output nodes to a third potential, which is between said first and second potentials, when the clock signal transits from the second level to the first level.