System for encoding an image control signal onto a pixel clock signal
First Claim
Patent Images
1. A system for encoding control data onto a clock signal comprising:
- at least one clock cycle in the clock signal;
a first transition in the at least one clock cycle, the first transition is from a first voltage level to a second voltage level, the first transition is in a first location in the at least one clock cycle;
a second transition in the at least one clock cycle, the second transition is from the second voltage level to the first voltage level, the second transition has a variable location in the clock cycle; and
an encoder circuit for positioning the second transition in the variable location in response to the control data;
wherein the control data comprises three control bits.
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Abstract
A system for encoding control data onto a clock signal includes at least one clock cycle in the clock signal; a first transition in the at least one clock cycle, the first transition is from a first voltage level to a second voltage level, the first transition is in a first location in the at least one clock cycle; a second transition in the at least one clock cycle, the second transition is from the second voltage level to the first voltage level, the second transition has a variable location in the clock cycle; and an encoder circuit for positioning the second transition in the variable location in response to the control data.
95 Citations
11 Claims
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1. A system for encoding control data onto a clock signal comprising:
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at least one clock cycle in the clock signal; a first transition in the at least one clock cycle, the first transition is from a first voltage level to a second voltage level, the first transition is in a first location in the at least one clock cycle; a second transition in the at least one clock cycle, the second transition is from the second voltage level to the first voltage level, the second transition has a variable location in the clock cycle; and an encoder circuit for positioning the second transition in the variable location in response to the control data; wherein the control data comprises three control bits. - View Dependent Claims (2, 3, 4)
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5. A device for transmitting video signals comprising:
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video signal bits having parallel image data bits and at least one control bit; at least one image serializer for converting the parallel image data bits to serial data; an encoder circuit for converting the at least one control bit to parallel clock encoding data; a control signal serializer for providing an encoded clock signal; and a clock signal for clocking the at least one image serializer and the control signal serializer. - View Dependent Claims (6, 7, 8, 9, 10)
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11. A method for transferring video signals comprising:
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encoding control data onto a clock signal to provide an encoded clock signal; converting parallel video data to serial data; transferring the serial data and the encoded clock signal through differential lines; converting the serial data on the differential lines to parallel data; and decoding the encoded clock signal to obtain the control data and the clock signal.
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Specification