System for encoding an image control signal onto a pixel clock signal

• US 5,859,669 A
• Filed: 11/26/1996
• Issued: 01/12/1999
• Est. Priority Date: 11/26/1996
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Prentice, Richard Mark
• Primary Examiner(s): Faile, Andrew I.
• Assistant Examiner(s): HOUSE, RONALD
• Application Number:
  US08/756,631
• Time in Patent Office: 777 Days
• Field of Search: 348/508, 348/512, 348/521, 348/524, 348/537, 348/538, 348/541, 348/213, 348/495, 348/500, 348/792, 348/791, 348/793, 348/469, 348/473, 327/175, 375/238, 375/239, 375/241, 375/359-364, 375/371-375, 345/99, 345/213, 345/214, 345/98, 370/205, 370/212, 370/537, 341/53, 341/182
• US Class Current: 348/469
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04
• CPC Class Codes: G09G 5/18 Timing circuits for raster scan displays specially adapted for television H04N ; synchronisation between the display unit and other display units, videodisc player G09G5/12

Abstract

A system for encoding control data onto a clock signal includes at least one clock cycle in the clock signal; a first transition in the at least one clock cycle, the first transition is from a first voltage level to a second voltage level, the first transition is in a first location in the at least one clock cycle; a second transition in the at least one clock cycle, the second transition is from the second voltage level to the first voltage level, the second transition has a variable location in the clock cycle; and an encoder circuit for positioning the second transition in the variable location in response to the control data.

Claims

1. A system for encoding control data onto a clock signal comprising:

at least one clock cycle in the clock signal;

a first transition in the at least one clock cycle, the first transition is from a first voltage level to a second voltage level, the first transition is in a first location in the at least one clock cycle;

a second transition in the at least one clock cycle, the second transition is from the second voltage level to the first voltage level, the second transition has a variable location in the clock cycle; and

an encoder circuit for positioning the second transition in the variable location in response to the control data;

wherein the control data comprises three control bits.

2. The system of claim 1 wherein the three control bits have five valid combinations.

3. The system of claim 2 wherein the variable location is one of five discrete locations.

4. The system of claim 3 wherein each of the five valid combinations are encoded onto a corresponding one of the five discrete locations.

5. A device for transmitting video signals comprising:

video signal bits having parallel image data bits and at least one control bit;

at least one image serializer for converting the parallel image data bits to serial data;

an encoder circuit for converting the at least one control bit to parallel clock encoding data;

a control signal serializer for providing an encoded clock signal; and

a clock signal for clocking the at least one image serializer and the control signal serializer.

6. The device of claim 5 further comprising at least one differential driver for receiving corresponding serial data from the at least one image serializer.

7. The device of claim 5 further comprising at least one latch for coupling the parallel image data bits to a corresponding at least one image serializer.

8. The device of claim 5 further comprising a differential driver for receiving the encoded clock signal.

9. The device of claim 5 further comprising a phase locked loop for providing the clock signal.

10. The device of claim 5 wherein the image serializers convert six parallel image bits to serial data.

11. A method for transferring video signals comprising:

encoding control data onto a clock signal to provide an encoded clock signal;

converting parallel video data to serial data;

transferring the serial data and the encoded clock signal through differential lines;

converting the serial data on the differential lines to parallel data; and

decoding the encoded clock signal to obtain the control data and the clock signal.