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Method and apparatus for real time two dimensional redundancy allocation

  • US 5,859,804 A
  • Filed: 09/26/1997
  • Issued: 01/12/1999
  • Est. Priority Date: 10/16/1991
  • Status: Expired due to Fees
First Claim
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1. An array built in self test (ABIST) system disposed on a single semiconductor chip comprisinga memory array having a plurality of column lines and a plurality of row lines and at least one redundant column line and at least one redundant row line with cells coupled to the lines at intersections thereof,first means coupled to said memory array for identifying a given number of faulty cells along each of said column lines,first register means having a number of registers equal to the number of redundant column lines,means for applying column address signals to said first register means,means coupled to said first identifying means for storing the address signals of each of the column lines having said given number of faulty cells in said first register means,second means coupled to said memory array for identifying a faulty cell along each of said row lines while masking the faulty cells having address signals of said column lines stored in said first register means,second register means having a number of registers equal to the number of redundant row lines,means for applying row address signals to said second register means,means coupled to said second identifying means for storing the address signals of each of the row lines having a faulty cell in said second register means until said second register means is filled to capacity and then storing the column line address signals of any additional faulty cells identified in said row lines in said first register means, andmeans coupled to said registers means for substituting said redundant column and row lines for the column and row lines having address signals stored in said first and second register means.

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