Method and apparatus for real time two dimensional redundancy allocation

• US 5,859,804 A
• Filed: 09/26/1997
• Issued: 01/12/1999
• Est. Priority Date: 10/16/1991
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Koch, Garrett Stephen, Hedberg, Erik Leigh
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US08/938,757
• Time in Patent Office: 473 Days
• Field of Search: 365/200, 365/201, 371/10.2, 371/10.3, 371/21.1
• US Class Current: 365/201
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/72 with optimized replacement algorithms

Abstract

A method and apparatus are provided in an array built in self test (ABIST) environment formed on a semiconductor chip having an array of memory cells arranged in columns and rows and column and row redundant lines which includes testing the array along the columns to identify a given number of faulty cells in each of the columns, storing the column addresses having the given number of faulty cells in first registers, further testing the array along the columns or rows to identify any additional faulty cells while masking the cells having the stored column addresses and storing the row addresses having the faulty cell in second registers until all of the second registers store row addresses, and after all of the second registers store row addresses, continue testing the array while masking the cells having the stored column or row addresses and storing the column addresses of any remaining additional faulty cell in any unused register of the first registers.

Claims

1. An array built in self test (ABIST) system disposed on a single semiconductor chip comprising

a memory array having a plurality of column lines and a plurality of row lines and at least one redundant column line and at least one redundant row line with cells coupled to the lines at intersections thereof,

first means coupled to said memory array for identifying a given number of faulty cells along each of said column lines,

first register means having a number of registers equal to the number of redundant column lines,

means for applying column address signals to said first register means,

means coupled to said first identifying means for storing the address signals of each of the column lines having said given number of faulty cells in said first register means,

second means coupled to said memory array for identifying a faulty cell along each of said row lines while masking the faulty cells having address signals of said column lines stored in said first register means,

second register means having a number of registers equal to the number of redundant row lines,

means for applying row address signals to said second register means,

means coupled to said second identifying means for storing the address signals of each of the row lines having a faulty cell in said second register means until said second register means is filled to capacity and then storing the column line address signals of any additional faulty cells identified in said row lines in said first register means, and

means coupled to said registers means for substituting said redundant column and row lines for the column and row lines having address signals stored in said first and second register means.

2. An array built in self test (ABIST) system disposed on a single semiconductor chip comprising,

a memory array having a first plurality of lines, a second plurality of lines arranged orthogonally with respect to said first plurality of lines and a plurality of redundant lines with elements coupled to the lines at intersections thereof,

first identifying means coupled to said memory array for identifying a given number of faulty elements along each of said lines of said first plurality of lines,

first address storage means,

means coupled to said first identifying means for storing address signals of each of the lines having said given number of faulty elements of said first plurality of lines in said first address storage means,

second identifing means coupled to said memory array for identifying a faulty cell along each of the lines of said second plurality of lines while masking the faulty elements having address signals of said first plurality of lines stored in said first address storage means,

second address storage means,

means coupled to said second identifying means for storing address signals of each of the lines of the second plurality of lines having a faulty element in said second address storage means until second storage address means is filled to capacity and then storing the address signals of any additional faulty element identified along the lines of said second plurality of lines in said first address storage means, and

means coupled to said first and second address storage means for substituting said plurality of redundant lines for the lines having address signals stored in said first and second address storage means.

3. An array built in self test (ABIST) system disposed on a single semiconductor chip comprising

a memory array disposed on said semiconductor chip having a plurality of column lines and a plurality of row lines and at least one redundant column line and at least one redundant row line with cells coupled to the lines at intersections thereof,

first means coupled to said memory array for identifying a given number of faulty cells along each of said column lines,

first register means disposed on said semiconductor chip having a number of registers equal to the number of redundant column lines,

means for applying column address signals to said first register means,

means coupled to said first identifying means for storing the address signals of each of the column lines having said given number of faulty cells in said first register means immediately upon identification of the given number of faulty cells along each of said column lines,

second means coupled to said memory array for identifying a faulty cell along each of said row lines while masking the faulty cells having address signals of said column lines stored in said first register means,

second register means disposed on said semiconductor chip having a number of registers equal to the number of redundant row lines,

means for applying row address signals to said second register means,

means coupled to said second identifying means for storing the address signals of each of the row lines having a faulty cell in said second register means immediately upon identification of the faulty cell along each of said row lines until said second register means is filled to capacity and then storing the column line address signals of any additional faulty cells identified in said row lines in said first register means, and

means coupled to said registers means for substituting said redundant column and row lines for the column and row lines having address signals stored in said first and second register means.

4. An array built in self test (ABIST) system disposed on a single semiconductor chip comprising,

a memory array having a first plurality of lines, a second plurality of lines arranged orthogonally with respect to said first plurality of lines and a plurality of redundant lines with elements coupled to the lines at intersections thereof,

first identifying means coupled to said memory array for identifying a given number of faulty elements along each of said lines of said first plurality of lines,

first address storage means disposed on said semiconductor chip,

means coupled to said first identifying means for storing address signals of each of the lines having said given number of faulty elements of said first plurality of lines in said first address storage means immediately upon identification of the given number of faulty elements along each of said lines of said first plurality of lines,

second identifying means coupled to said memory array for identifying a faulty element along each of the lines of said second plurality of lines while masking the faulty elements having address signals of said first plurality of lines stored in said first address storage means,

second address storage means disposed on said semiconductor chip,

means coupled to said second identifying means for storing address signals of each of the lines of the second plurality of lines having a faulty element in said second address storage means until second storage address means is filled to capacity and then storing the address signals of any additional faulty element identified along the lines of said second plurality of lines in said first address storage means immediately upon identification of the faulty element along each of the lines of said second plurality of lines, and

means coupled to said first and second address storage means for substituting said plurality of redundant lines for the lines having address signals stored in said first and second address storage means.