Fully-interconnected asynchronous transfer mode switching apparatus
First Claim
1. A fully-interconnected asynchronous transfer mode switching apparatus comprising:
- a plurality of line interface means, each of said plurality of line interface means including input port drive means for converting an input optical signal into an electrical signal, recovering a clock signal from the converted electrical signal, extracting a synchronous digital hierarchy transmission frame from the converted electrical signal in response to the recovered clock signal, the extracted synchronous digital hierarchy transmission frame containing cell data with a fixed length and a connection identifier, appending a routing tag to the extracted synchronous digital hierarchy transmission frame to produce a resultant synchronous digital hierarchy transmission frame, outputting the resultant synchronous digital hierarchy transmission frame and the recovered clock signal through an input dedicated bus, extracting a signalling cell or a network managing cell terminating at the apparatus from the converted electrical signal and outputting the extracted signalling cell or network managing cell through a first internal dedicated bus, and output port drive means for receiving a cell stream from an output dedicated bus, removing the routing tag from the received cell stream, translating a channel identifier in the connection identifier, transferring the resultant synchronous digital hierarchy transmission frame to an adjacent node, receiving the signalling cell or the network managing cell from a second internal dedicated bus and transferring the received signalling cell or network managing cell to the adjacent node;
system clock distribution means for receiving the recovered clock signal from said input port drive means in each of said plurality of line interface means through a clock dedicated bus, providing a clock signal synchronously with the received clock signal and according to network synchronous system and structure and distributing its self-clock signal if an error is temporarily present in the received clock signal;
initialization control means for controlling system initialization and restart operations;
switch maintenance control means for performing an entire system initialization control operation in response to initialization information and a control signal from said initialization control means and performing a switch maintenance control operation in response to the network managing cell from said input port drive means in each of said plurality of line interface means;
switch call processing control means for receiving the signalling cell or the network managing cell from said input port drive means in each of said plurality of line interface means through said first internal dedicated bus, preprocessing the received signalling cell or network managing cell, outputting the preprocessed cell to said switch maintenance control means if the received cell is the network managing cell, performing a call processing operation by analyzing a message of the preprocessed cell if the received cell is the signalling cell and outputting connection information containing a channel identifier and a routing tag to each of said plurality of line interface means when a connection is set based on the call processing operation;
switch module control means for receiving the clock signal from said system clock distribution means, performing an initialization operation under the control of said initialization control means, outputting a control signal through a control dedicated bus under the control of said switch maintenance control means, checking operation and malfunction states, reporting the checked result to said switch maintenance control means and performing a duplexed function of replacing a faulty switch board with a normal switch board; and
a plurality of switch output multiplexing means, each of said plurality of switch output multiplexing means receiving successive cells from said input port drive means in said plurality of line interface means through said input dedicated buses, each of the received cells containing cell data, a cell enable signal, a start-of-cell signal and a synchronous clock signal, temporarily storing the received cells, performing a received cell selection operation to preferentially read the stored cells corresponding to ones of said input port drive means with high generation frequency and outputting the read cells through said output dedicated bus under the control of said switch module control means.
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Abstract
A fully-interconnected ATM switching apparatus comprising a plurality of line interface circuits, each of the line interface circuits including an input port driver for extracting an SDH transmission frame containing cell data with a fixed length and a connection identifier from an input signal, appending a routing tag to the extracted SDH transmission frame and outputting the resultant SDH transmission frame through an input dedicated bus and an output port driver for receiving a cell stream from an output dedicated bus, removing the routing tag from the received cell stream, translating a channel identifier in the connection identifier and transferring the resultant SDH transmission frame to an adjacent node, a system clock distributor for generating a clock signal, an initialization controller for controlling system initialization and restart operations, a switch maintenance controller for performing a switch maintenance control operation in response to a network managing cell, a switch call processing controller for performing a call processing operation, a switch module controller for controlling a switching operation, and a plurality of switch output multiplexers for switching cells from the input port drivers to the output port drivers under the control of the switch module controller.
107 Citations
14 Claims
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1. A fully-interconnected asynchronous transfer mode switching apparatus comprising:
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a plurality of line interface means, each of said plurality of line interface means including input port drive means for converting an input optical signal into an electrical signal, recovering a clock signal from the converted electrical signal, extracting a synchronous digital hierarchy transmission frame from the converted electrical signal in response to the recovered clock signal, the extracted synchronous digital hierarchy transmission frame containing cell data with a fixed length and a connection identifier, appending a routing tag to the extracted synchronous digital hierarchy transmission frame to produce a resultant synchronous digital hierarchy transmission frame, outputting the resultant synchronous digital hierarchy transmission frame and the recovered clock signal through an input dedicated bus, extracting a signalling cell or a network managing cell terminating at the apparatus from the converted electrical signal and outputting the extracted signalling cell or network managing cell through a first internal dedicated bus, and output port drive means for receiving a cell stream from an output dedicated bus, removing the routing tag from the received cell stream, translating a channel identifier in the connection identifier, transferring the resultant synchronous digital hierarchy transmission frame to an adjacent node, receiving the signalling cell or the network managing cell from a second internal dedicated bus and transferring the received signalling cell or network managing cell to the adjacent node; system clock distribution means for receiving the recovered clock signal from said input port drive means in each of said plurality of line interface means through a clock dedicated bus, providing a clock signal synchronously with the received clock signal and according to network synchronous system and structure and distributing its self-clock signal if an error is temporarily present in the received clock signal; initialization control means for controlling system initialization and restart operations; switch maintenance control means for performing an entire system initialization control operation in response to initialization information and a control signal from said initialization control means and performing a switch maintenance control operation in response to the network managing cell from said input port drive means in each of said plurality of line interface means; switch call processing control means for receiving the signalling cell or the network managing cell from said input port drive means in each of said plurality of line interface means through said first internal dedicated bus, preprocessing the received signalling cell or network managing cell, outputting the preprocessed cell to said switch maintenance control means if the received cell is the network managing cell, performing a call processing operation by analyzing a message of the preprocessed cell if the received cell is the signalling cell and outputting connection information containing a channel identifier and a routing tag to each of said plurality of line interface means when a connection is set based on the call processing operation; switch module control means for receiving the clock signal from said system clock distribution means, performing an initialization operation under the control of said initialization control means, outputting a control signal through a control dedicated bus under the control of said switch maintenance control means, checking operation and malfunction states, reporting the checked result to said switch maintenance control means and performing a duplexed function of replacing a faulty switch board with a normal switch board; and a plurality of switch output multiplexing means, each of said plurality of switch output multiplexing means receiving successive cells from said input port drive means in said plurality of line interface means through said input dedicated buses, each of the received cells containing cell data, a cell enable signal, a start-of-cell signal and a synchronous clock signal, temporarily storing the received cells, performing a received cell selection operation to preferentially read the stored cells corresponding to ones of said input port drive means with high generation frequency and outputting the read cells through said output dedicated bus under the control of said switch module control means. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A fully-interconnected asynchronous transfer mode switching apparatus comprising:
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a plurality of line interface means, each of said line interface means including input port processing means for extracting fixed length cell data with a control header from a transmission frame, for translating the control header to an internal connection identifier, for constructing a new internal cell data by appending routing tag information to the front of the cell data for cell switching, and for transmitting said internal cell data through an input dedicated bus, and output port processing means for receiving said internal cell data, for removing said routing tag from said internal data, for translating said internal connection identifier to a new control header in transmitting cell data, and for transmitting the cell data to an adjacent network system via said transmission frame; a plurality of switch output multiplexing means, each of said plurality of switch output multiplexing means for receiving successive internal cell data from said input port processing means in said line interface means via said input dedicated bus, for filtering only internal cell data with a corresponding output port address from the cell data, for temporarily storing said filtered cell data in dedicated internal buffers into a cell data stream in order of higher cell occupied degree at a higher speed, for storing the multiplexed cell data temporarily into an output shared buffer for speed adaptation, and for transmitting said cell data in said output shared buffer to said output port processing means; system clock distribution means for receiving a network synchronization clock and recovered clock signals from said input port processing means, for selecting a most stable clock signal among said recovered clock signals, and for distributing said selected clock signal; initialization control means for controlling system initialization and restart operations; switch maintenance control means for performing an entire system operation and management function in response to a control signal from said initialization control means and network management cell data extracted from said line interface means; switch call processing control means for performing call processing and connection control function according to an extracted signalling cell data from said line interface means; and switch module control means for controlling said switch output multiplexing means in response to the control signal from said switch maintenance control means. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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Specification