Arrangement, system, and method for automatic remapping of frame buffers when switching operating modes

• US 5,860,016 A
• Filed: 09/30/1996
• Issued: 01/12/1999
• Est. Priority Date: 09/30/1996
• Status: Expired due to Fees

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Sponring, Otto, Sivamani, Kameswaran, Nookala, Narasimha R.
• Primary Examiner(s): An, Meng-Ai T.
• Assistant Examiner(s): Etienne, Ario
• Application Number:
  US08/720,392
• Time in Patent Office: 834 Days
• Field of Search: 395/750.01-750.08, 364/492, 711/104, 711/105, 711/106
• US Class Current: 713/324
• CPC Class Codes: G09G 2330/022 in absence of operation, e.g. no data being entered during a predetermined time
• CPC Class Codes: G09G 2340/0428 Gradation resolution change
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers

Abstract

An arrangement, system, and method to allow a computer system to have a normal operating mode with full display capability and a low-power operating mode with reduced display capability is provided. The computer system automatically switches to the low-power operating mode from the normal operating mode following a programmable period of inactivity. While display data is retrieved from an external DRAM in the normal operating mode, display data is retrieved from an internal SRAM in the low-power operating mode. The computer system switches back to the normal operating mode when one of the predetermined activities is detected.

Claims

1. An apparatus to allow a computer system to have both a normal operating mode having full display capability and a low-power operating mode having a reduced display capability, comprising:

a main state machine, the main state machine generating a plurality of control signals to indicate whether the normal operating mode or the low-power operating mode is in effect;

internal memory;

external memory;

a memory controller coupled to the main state machine, the internal memory, and the external memory, the memory controller switching to the internal memory as a source of display data when operating in the low-power operating mode and to the external memory as a source of display data when operating in the normal operating mode in response to a first control signal from the main state machine; and

a display controller coupled to the memory controller and the main state machine, the display controller comprising a pallette and a gray scaling logic to provide enhanced color data in the normal operating mode, the display controller initiating a request to the memory controller to fetch for display data in response to a second control signal from the main state machine, the memory controller fetching display data from the internal memory or the external memory in response to the request, upon receiving the display data the display controller outputting the display data, wherein the display data bypasses the pallette and gray scaling logic in the low-power operating mode, the display controller switches off the pallette and the gray scaling logic in the low-power operating mode.

2. The arrangement of claim 1 further comprising a timer circuit coupled to the main state machine, the timer circuit monitoring a period of inactivity, the timer circuit indicating to the main state machine when the period of inactivity expires thereby signifying to the main state machine that the low-power operating mode is in effect.

3. The arrangement of claim 2 further comprising an interrupt controller coupled to the main state machine, the interrupt controller monitoring predetermined activities, the interrupt controller indicating to the main state machine when any of the predetermined activities occurs, the main state machine resetting the timer circuit when any of the predetermined activities occurs.

4. The arrangement of claim 3 further comprising a power management circuit coupled to the main state machine, the power management circuit providing a system clock signal to predetermined modules upon receiving a third control signals from the main state machine indicating that the low-power operating mode is in effect.

5. The arrangement of claim 1, wherein the internal memory is static random access memory.

6. The arrangement of claim 1, wherein the external memory is dynamic random access memory.

7. The arrangement of claim 6, wherein the memory controller putting the external memory in a self-refresh mode during the low-power operating mode.

8. A computer system having a normal operating mode with full display and a low-power operating mode with reduced display comprising:

a display;

external memory;

an input device;

a main controller coupled to the display, the external memory, and the input device, the main controller comprising;

a central processing unit (CPU);

a main state machine, the main state machine generating a plurality of control signals to indicate whether the normal operating mode or the low-power operating mode is in effect;

internal memory;

a memory controller coupled to the main state machine, the internal memory, and the external memory, the memory controller switching to the internal memory as a source of display data when operating in the low-power operating mode and to the external memory as a source of display data when operating in the normal operating mode in response to a first control signal from the main state machine; and

a display controller coupled to the memory controller and the main state machine, the display controller comprising a pallette and a gray scaling logic to provide enhanced color data in the normal operating mode, the display controller initiating a request to the memory controller to fetch for display data in response to a second control signal from the main state machine, the memory controller fetching display data from the internal memory or the external memory in response to the request, upon receiving the display data the display controller outputting the display data, wherein the display data bypasses the pallette and gray scaling logic in the low-power operating mode, the display controller switches off the pallette and the gray scaling logic in the low-power operating mode.

9. The computer system of claim 8, wherein the main controller further comprising a timer circuit coupled to the main state machine, the timer circuit monitoring a period of inactivity, the timer circuit indicating to the main state machine when the period of inactivity expires thereby signifying to the main state machine that the low-power operating mode is in effect.

10. The computer system of claim 9, wherein the main controller further comprising an interrupt controller coupled to the main state machine, the interrupt controller monitoring predetermined activities, the interrupt controller indicating to the main state machine when any of the predetermined activities occurs, the main state machine resetting the timer circuit when any of the predetermined activities occurs.

11. The computer system of claim 10, wherein the main controller further comprising a power management circuit coupled to the main state machine, the power management circuit providing a system clock signal to predetermined modules upon receiving a third control signals from the main state machine indicating that the low-power operating mode is in effect.

12. The computer system of claim 8, wherein the internal memory is static random access memory.

13. The computer system of claim 8, wherein the external memory is dynamic random access memory.

14. The computer system of claim 13, wherein the memory controller putting the external memory in a self-refresh mode during the low-power operating mode.

15. A method for switching from a normal operating mode having full display to a low-power operating mode having reduced display in a computer system comprising a plurality of module, the method comprising:

a) setting a timer;

b) resetting the timer when predetermined activities occur;

c) when the timer expires, waiting for any on-going activity to complete;

d) shutting off a system clock signal to predetermined modules;

e) waiting for an active display to be completed;

f) putting an external RAM from which display data are being retrieved on self refresh mode;

g) switching display data source from the external RAM to an internal RAM;

h) retrieving display data from the internal RAM;

i) turning off circuitry designed to enhance display data color during the normal operating mode; and

j) sending the display data directly to display monitor and bypassing the display data color enhancing circuitry.

16. The method of claim 15, wherein to switch back from the low-power operating mode having reduced display to the normal operating mode having full display, the method further comprising:

k) turning on the system clock signal to all modules;

l) waiting for an active display to be completed;

m) bringing the external RAM out of self-refresh mode;

n) switching display data source from the internal RAM to the external RAM;

o) retrieving display data from the external RAM;

p) turning on circuitry designed to enhance display data color during the normal operating mode, and

q) sending the display data through the display data color enhancing circuitry to display monitor.