Single chip microcontroller having down-loadable memory organization supporting "shadow" personality, optimized for bi-directional data transfers over a communication channel

• US 5,860,021 A
• Filed: 04/24/1997
• Issued: 01/12/1999
• Est. Priority Date: 04/24/1997
• Status: Expired due to Term

• Current Assignee: SK Hynix Inc.
• Original Assignee: Edwin E. Klingman
• Inventors: Klingman, Edwin E.
• Primary Examiner(s): SHAH, ALPESH
• Application Number:
  US08/846,118
• Time in Patent Office: 628 Days
• Field of Search: 395/800.01, 395/800.32, 395/200.43, 395/200.08, 395/200.5, 395/828, 395/309, 711/100, 711/131, 711/147, 711/139, 370/254, 370/351, 370/401, 370/402
• US Class Current: 712/32
• CPC Class Codes: H04L 12/40123 Interconnection of computers and peripherals printer information exchange with computer G06F3/1293
• CPC Class Codes: H04Q 11/0435 Details

Abstract

A microcontroller down-loadable memory organization supporting "shadow" personality, optimized for connecting a computer system to an ISDN network to facilitate transmitting and receiving of data, the microcontroller including a processor and a memory structure having ROM memory space for storing program code therein and further including a dual port RAM for connection between the computer and the processor, the dual port RAM having RAM memory space for storing program code therein and shared RAM for storing data capable of being simultaneously accessible by the processor and the computer, wherein the program ROM and the program RAM are selectively used by the computer to store program code by the computer using a ROM/RAM* select signal, and wherein the starting address in the shared RAM wherein data is stored is selectably offset from the starting address of the code RAM and the code ROM.

Claims

1. A microcontroller integrated circuit for connecting a computer system having a host processor to an ISDN interface to accommodate data transfer over an ISDN network, comprising:

a local processor; and

a dual port RAM addressable by the host processor and said local processor and having a predetermined first memory space for storing program code and a predetermined second memory space for storing data,

whereby the host processor and said local processor can simultaneously access said second memory space and the host processor can further access said first and second memory spaces when it resets said local processor while said local processor is in reset and when said local processor is not in reset, said local processor can access said first and second memory spaces.

2. A microcontroller integrated circuit as recited in claim 1 wherein said local processor further includes a reset input terminal responsive to a reset signal from the host processor for resetting said local processor when said reset signal is in an active state and for releasing said local processor from reset when said reset signal is not in an active state.

3. A microcontroller integrated circuit as recited in claim 2 wherein the host processor is prevented from accessing said first memory space when said reset signal is not activated.

4. A microcontroller integrated circuit as recited in claim 1 wherein said second memory space of said dual port RAM further includes a local control register responsive to a predetermined value provided by the host processor for resetting said local processor when said predetermined value is received by said local control register and for releasing said local register from reset when the host processor provides a value other than the predetermined value to said local control register.

5. A microcontroller integrated circuit as recited in claim 4 wherein the host processor is prevented from accessing said first memory space during the period in which said local processor is reset.

6. A microcontroller integrated circuit as recited in claim 1 further including a program ROM coupled between the host processor and said local processor for alternatively storing program code wherein while said local processor is in reset the host processor selectably stores program code in a group consisting of said dual port RAM and said program ROM depending upon the state of a ROM/RAM* signal applied to said local processor.

7. A microcontroller integrated circuit as recited in claim 6 wherein said ROM/RAM* signal is programmed by the host processor.

8. A microcontroller integrated circuit as recited in claim 7 wherein said ROM/RAM* signal is a constant value indicating the selection of said program ROM.

9. A microcontroller integrated circuit as recited in claim 6 wherein said local processor executes program code from a group consisting of said dual port RAM and said program ROM depending upon the state of said ROM/RAM* signal.

10. A microcontroller integrated circuit as recited in claim 1 wherein said local processor further includes an internal data RAM for storing data, said internal data RAM accessible only by said local processor.

11. A microcontroller integrated circuit as recited in claim 1 further including an external data RAM coupled externally to the microcontroller integrated circuit through local processor signals generated by the local processor for storing data in said external RAM when the maximum addressable location of said dual port RAM is exceeded.

12. A microcontroller for facilitating transfer of digital information from a host processor through a communication channel, comprising:

a local processor;

a program ROM having storage locations addressable by said local processor, said program ROM for storing program code;

a dual port RAM having storage locations addressable by the host processor and said local processor and having a predetermined storage area for storing data, said data storage area being simultaneously accessible by the local processor and the host processor,

whereby the host processor and said local processor can simultaneously access said data storage area and the host processor can further access said program storage area and said data storage when said local processor is in reset, and when said local processor is not in reset, said local processor can access said data storage space and said program storage space.

13. A microcontroller as recited in claim 12 wherein said ROM and RAM are addressed by the host through host address signals, host data signals, host bus control signal, and host interrupt signals.

14. A microcontroller as recited in claim 12 wherein said local processor is operative to generate local processor address signals for addressing the storage locations within said ROM and said RAM.

15. A microcontroller as recited in claim 14 and further including a comparator circuit responsive to said host address signals and said local processor address signals for comparing said host address signals to said local processor address signals, said comparator circuit operative to generate a wait signal for use by the host processor, wherein when said local address signals and said host address signals are the same, the wait signal is activated causing the host processor to wait for accessing said RAM, and when the local processor address signals and the host address signals are not the same, the wait signal is deactivated, allowing the host processor to freely access the RAM.

16. A microcontroller as recited in claim 15 further including an external memory coupled externally to the local processor and responsive to said local processor address signals for storing binary data when said local processor address exceeds a maximum internal data address.

17. A microcontroller as recited in claim 16 wherein the local processor includes an ALU circuit responsive to local processor data signals and operative to generate an ALU output signals, a special function register circuit responsive to said ALU output signals and operative to generate output program counter signals, a program counter circuit responsive to said output program counter signals and to said local processor data signals and operative to generate next local processor data signals, and a control circuit responsive to said next local processor data signals and operative to generate a plurality of control signals for use by the local processor, wherein program code having a series of program instructions is executed from either of said ROM or RAM with the order of execution of the program instructions being defined by said program counter under the direction of said control circuit to configure said ALU to process the local processor data signals.