Video processor with serialization FIFO

• US 5,860,086 A
• Filed: 06/04/1997
• Issued: 01/12/1999
• Est. Priority Date: 06/07/1995
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Pancoast, Steve T., Crump, Dwayne T.
• Primary Examiner(s): Chan, Eddie P.
• Assistant Examiner(s): KIM, HONG CHONG
• Application Number:
  US08/868,778
• Time in Patent Office: 587 Days
• Field of Search: 711/1, 711/123, 711/109, 711/110, 345/28, 345/193, 345/515, 345/516, 345/502, 345/501, 345/519, 375/372, 395/800.1, 395/386, 341/67, 371/37.05, 382/246, 364/725.03, 364/725.01
• US Class Current: 711/109
• CPC Class Codes: G09G 2340/02 Handling of images in compressed format, e.g. JPEG, MPEG
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/61 in combination with predictive coding

Abstract

A digital data handling system handling display signal streams has a video processor which is capable of high performance due to vector processing and special addressing modes. The video processor is a single VLSI device having a plurality of processors, each of which has associated instruction and data caches, which are joined together by a wide data bus formed on the same substrate as the processors. Most audio and/or video compression algorithms use a Huffman style bit compression scheme with compression codes in variable length bit fields. The compressed data is a compacted bit stream which must be interpreted serially in order to extract the codes. In contrast to most microprocessors which process bit streams only inefficiently, the present invention uses a serialization FIFO to provide a hardware assist to the Huffman encoding/decoding.

Claims

1. An integrated circuit device comprising:

a substrate,

a plurality of identical processors formed on said substrate,

each of said processors having an instruction cache, a data cache, a bus interface unit, and an arithmetic logic unit;

a line bus formed on said substrate and interconnecting all of said plurality of processors for transferring data bit streams thereamong;

a video input interface unit formed on said substrate and connected to said line bus for receiving an input signal stream;

a video output interface unit formed on said substrate and connected to said line bus for delivering from the integrated circuit device an output video signal stream determined from processing by said plurality of processors;

a host interface unit formed on said substrate and connected to said line bus for exchanging with a host processor control signals effective for governing the function of said plurality of processors;

a control bus formed on said substrate and interconnecting said host interface unit and said plurality of processors for exchange of control and data signals therewith apart from data bit streams transferred over said line bus;

a memory interface unit formed on said substrate and connected to said line bus for exchanging with memory elements data bit streams processed and to be processed by said plurality of processors;

a serialization circuit interposed between said control bus and one of said processors for receiving and delivering data streams transferred with said control bus in parallel, fixed bit width transfers, for shifting the positions of bits in the data streams, and for transferring serial bit streams of varying length with said one of said processors.

2. The device of claim 1, wherein said varying length is not solely a multiple of eight.

3. An integrated circuit device comprising:

a substrate,

a plurality of identical processors formed on said substrate,

each of said processors having an instruction cache, a data cache, a bus interface unit, and an arithmetic logic unit;

a line bus formed on said substrate and interconnecting all of said plurality of processors for transferring data bit streams thereamong;

a video input interface unit formed on said substrate and connected to said line bus for receiving an input signal stream;

a video output interface unit formed on said substrate and connected to said line bus for delivering from the integrated circuit device an output video signal stream determined from processing by said plurality of processors;

a host interface unit formed on said substrate and connected to said line bus for exchanging with a host processor control signals effective for governing the function of said plurality of processors;

a control and data bus formed on said substrate and interconnecting said host interface unit and said plurality of processors for exchange of control signals therewith apart from data bit streams transferred over said line bus;

a memory interface unit formed on said substrate and connected to said line bus for exchanging with memory elements data bit streams processed and to be processed by said plurality of processors;

a serialization FIFO register interposed between said control bus and one of said processors for receiving and delivering data streams transferred in parallel, fixed bit width transfers;

a barrel shifter interposed between said serialization FIFO register and said one of said processors for shifting the positions of bits in the data streams delivered to and received from said serialization FIFO; and

a serialization register interposed between said barrel shifter and said one of said processors for transferring serial bit streams of varying length between said one of said processors and said barrel shifter.

4. The device of claim 3, wherein said varying length is not solely a multiple of eight.

5. A system for handling digital data and generating video display signals, the system comprising:

a central processing unit;

system random access memory for receiving and storing and delivering digital data;

a bus interconnecting said central processing unit and said system random access memory for transferring digital data signals; and

a video processor integrated circuit device operatively connected to said bus and thereby to said central processing unit and to said system random access memory, said video processor integrated circuit device processing video display signals under the direction of said central processing unit and having;

a substrate,

a plurality of identical processors formed on said substrate,

each of said processors having an instruction cache, a data cache, a bus interface unit, and an arithmetic logic unit;

a line bus formed on said substrate and interconnecting all of said plurality of processors for transferring data bit streams thereamong;

a video input interface unit formed on said substrate and connected to said line bus for receiving an input signal stream;

a video output interface unit formed on said substrate and connected to said line bus for delivering from the integrated circuit device an output video signal stream determined from processing by said plurality of processors;

a host interface unit formed on said substrate and connected to said line bus for exchanging with a host processor control signals effective for governing the function of said plurality of processors;

a control bus formed on said substrate and interconnecting said host interface unit and said plurality of processors for exchange of control and data signals therewith apart from data bit streams transferred over said line bus;

a memory interface unit formed on said substrate and connected to said line bus for exchanging with memory elements data bit streams processed and to be processed by said plurality of processors;

a serialization circuit interposed between said control bus and one of said processors for receiving and delivering data streams transferred with said control bus in parallel, fixed bit width transfers, for shifting the positions of bits in the data streams, and for transferring serial bit streams of varying length with said one of said processors.

6. The system of claim 5, wherein said varying length is not solely a multiple of eight.

7. A system for handling digital data and generating video display signals, the system comprising:

a central processing unit;

system random access memory for receiving and storing and delivering digital data;

a bus interconnecting said central processing unit and said system random access memory for transferring digital data signals; and

a video processor integrated circuit device operatively connected to said bus and thereby to said central processing unit and to said system random access memory, said video processor integrated circuit device processing video display signals under the direction of said central processing unit and having;

a substrate,

a plurality of identical processors formed on said substrate,

each of said processors having an instruction cache, a data cache, a bus interface unit, and an arithmetic logic unit;

a line bus formed on said substrate and interconnecting all of said plurality of processors for transferring data bit streams thereamong;

a video input interface unit formed on said substrate and connected to said line bus for receiving an input signal stream;

a video output interface unit formed on said substrate and connected to said line bus for delivering from the integrated circuit device an output video signal stream determined from processing by said plurality of processors;

a host interface unit formed on said substrate and connected to said line bus for exchanging with a host processor control signals effective for governing the function of said plurality of processors;

a control bus formed on said substrate and interconnecting said host interface unit and said plurality of processors for exchange of control and data signals therewith apart from data bit streams transferred over said line bus;

a memory interface unit formed on said substrate and connected to said line bus for exchanging with memory elements data bit streams processed and to be processed by said plurality of processors;

a serialization FIFO register interposed between said control bus and one of said processors for receiving and delivering data streams transferred in parallel, fixed bit width transfers;

a barrel shifter interposed between said serialization FIFO register and said one of said processors for shifting the positions of bits in the data streams delivered to and received from said serialization FIFO; and

a serialization register interposed between said barrel shifter and said one of said processors for transferring serial bit streams of varying length between said one of said processors and said barrel shifter.

8. The system of claim 7, wherein said varying length is not solely a multiple of eight.