Stored program system with protected memory and secure signature extraction

• US 5,860,099 A
• Filed: 05/12/1993
• Issued: 01/12/1999
• Est. Priority Date: 05/12/1993
• Status: Expired due to Term

• Current Assignee: Usarsys Acquisition Corp. (Semtech Corporation)
• Original Assignee: Usar Systems Incorporated (Semtech Corporation)
• Inventors: Milios, Ioannis, Oppedahl, Carl
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): Thai, Tuan V.
• Application Number:
  US08/061,203
• Time in Patent Office: 2,071 Days
• Field of Search: 264/200, 95/400, 395/425, 395/430, 395/490, 395/725, 395/491, 395/492, 380/4, 380/3
• US Class Current: 711/103
• CPC Class Codes: G06F 12/1408 by using cryptography for digital transmission H04L9/00
• CPC Class Codes: H04L 2209/605 Copy protection
• CPC Class Codes: H04L 9/3247 involving digital signatures

Abstract

A controller contains software which, when triggered in some prearranged way such as assertion of an input to the controller, calculates a digital signature for the contents of the protected memory of the controller. The digital signature is preferably extracted from the contents of the memory with a function that varies greatly with even small changes to the memory contents. The function preferably is such that one cannot easily determine from the output what input generated the output. The function is preferably such that one cannot easily create a data set for input that yields any particular predetermined output. The circuitry generating the signature may be embedded in hardware of the controller so that its digital signature function is unknown even to the programmer writing the main body of code to be stored in the protected memory. With such a hardware configuration, it is possible to have a very high degree of confidence that the memory contents are what they are expected to be.

Claims

1. A stored program system comprising a processor within an integrated circuit;

a bus operatively coupled with the processor;

a memory within the integrated circuit and coupled with the bus from which the processor fetches instructions, said memory having contents;

protection means within the integrated circuit and operatively coupled with the memory and with the bus, said protection means rendering the memory not readily readable by a user;

input means within the integrated circuit receiving an input external to the integrated circuit and generating a signal indicative thereof;

signature extraction means within the integrated circuit and operatively coupled with the memory, said signature extraction means responsive to the signal for reading substantially all the contents of the memory via the bus and extracting a signature reflective thereof; and

output means within the integrated circuit and operatively coupled with the signature extraction means and responsive to extraction of the signature for communicating the signature external to the integrated circuit, wherein the signature extraction means comprises the processor executing a stored program stored within the memory, wherein the stored program comprises a routine evaluating a polynomial taking bytes of data from the memory as input, each byte having an address, the polynomial having at least one coefficient that is large relative to the value of the bytes, the stored program further comprising repeatedly subtracting a prime number smaller than the at least one coefficient.

2. The system of claim 1 wherein the polynomial also takes as input the addresses from which the bytes of data are taken.

3. A stored program system comprising a processor within an integrated circuit;

a bus operatively coupled with the processor;

a memory within the integrated circuit and coupled with the bus from which the processor fetches instructions, said memory having contents;

protection means within the integrated circuit and operatively coupled with the memory and with the bus, said protection means rendering the memory not readily readable by a user;

input means within the integrated circuit receiving an input external to the integrated circuit and generating a signal indicative thereof;

signature extraction means within the integrated circuit and operatively coupled with the memory, said signature extraction means responsive to the signal for reading substantially all the contents of the memory via the bus and extracting a signature reflective thereof; and

output means within the integrated circuit and operatively coupled with the signature extraction means and responsive to extraction of the signature for communicating the signature external to the integrated circuit, wherein the signature extraction means comprises circuitry within the integrated circuit and apart from the processor, wherein the circuitry evaluates a function comprising a polynomial taking bytes of data from the memory as input, the polynomial having at least one coefficient that is large relative to the value of the bytes, the function further comprising a modulo function with respect to a prime number smaller than the coefficient.

4. The system of claim 3 wherein the polynomial also takes as input the addresses from which the bytes of data are taken.