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Method and apparatus for dynamically adjusting power/performance characteristics of a memory subsystem

  • US 5,860,106 A
  • Filed: 07/13/1995
  • Issued: 01/12/1999
  • Est. Priority Date: 07/13/1995
  • Status: Expired due to Fees
First Claim
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1. A computer system comprising:

  • a processor;

    a memory system including a cache;

    at least one bus coupled to the memory system and to the processor; and

    an optimization logic that predicts a probability of an event in a memory subsystem wherein the optimization logic enables a tag array if the probability of the event reaches a first predetermined level, enables a data cache if the probability of the event reaches a second predetermined level and only enables the data cache if the event actually occurs if the probability of the event has not reached the second predetermined level.

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