Method and apparatus for dynamically adjusting power/performance characteristics of a memory subsystem

• US 5,860,106 A
• Filed: 07/13/1995
• Issued: 01/12/1999
• Est. Priority Date: 07/13/1995
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Gunther, Stephen H., Domen, Stanley J., Thangadurai, George, Idate, Dileep R.
• Primary Examiner(s): Chan, Eddie P.
• Assistant Examiner(s): KIM, HONG CHONG
• Application Number:
  US08/502,094
• Time in Patent Office: 1,279 Days
• Field of Search: 365/227, 395/449, 395/750, 395/432, 395/438, 395/494, 395/486, 395/750.02, 395/750.03, 395/750.05, 395/750.06, 395/750.07, 395/750.01, 711/204, 711/213, 711/3, 711/154, 364/707
• US Class Current: 713/324
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An apparatus and method for dynamically adjusting the power/performance characteristics of a memory subsystem. Since the memory subsystem access requirements are heavily dependent on the application being executed, static methods of enabling or disabling the individual memory system components (as are used in prior art) are less than optimal from a power consumption perspective. By dynamically tracking the behavior of the memory subsystem, the invention predicts the probability that the next event will have certain characteristics, such as whether it will result in a memory cycle that requires the attention of a cache memory, whether that memory cycle will result in a cache memory hit, and whether a DRAM page hit in main memory will occur if the requested data is not in one of the levels of cache memory. Based on these probabilities, the invention dynamically enables or disables components of the subsystem. By intelligently adjusting the state of these components, significant power savings are achieved without degradation in performance.

Claims

1. A computer system comprising:

a processor;

a memory system including a cache;

at least one bus coupled to the memory system and to the processor; and

an optimization logic that predicts a probability of an event in a memory subsystem wherein the optimization logic enables a tag array if the probability of the event reaches a first predetermined level, enables a data cache if the probability of the event reaches a second predetermined level and only enables the data cache if the event actually occurs if the probability of the event has not reached the second predetermined level.

2. The computer system of claim 1 wherein the optimization logic comprises:

a plurality of comparators; and

a plurality of counters for tracking parameters coupled to the plurality of comparators which together predict the probability of an event in the memory subsystem wherein the parameters tracked include bus utilization and hit/miss occurrences for a portion of the memory subsystem.

3. The computer system of claim 1 wherein the memory subsystem comprises a main memory and the optimization logic dynamically enables a memory access mode to be one of page mode and single access mode base on a predicted probability of a second event.

4. A computer system comprising:

a processor;

a memory system;

at least one bus;

means for tracking behavior of a memory subsystem;

means for predicting the occurrence of an event in the memory subsystem based on the tracked behavior; and

means for dynamically adjusting a mode of operation of the memory subsystem responsive to the predicting means wherein the means for dynamically adjusting enables a tag array if the probability of the event reaches a first predetermined level, enables a data cache if the probability of the event reaches a second predetermined level, and only enables the data cache if the event actually occurs if the probability of the event has not reached the second predetermined level.

5. A method of dynamically adjusting characteristics of a computer system having a processor coupled to a memory subsystem including a cache, comprising the steps of:

recording information of prior activity of the memory subsystem;

predicting a probability of a cache hit on a next transaction with the cache;

enabling a tag array if the probability of a cache hit reaches a predetermined level;

enabling a data cache if the hit probability reaches a second predetermined level; and

enabling the data cache only if a hit actually occurs if the hit probability has not reached the second predetermined level.

6. The method of claim 5 wherein the memory subsystem comprises a memory organized in pages and wherein the method further comprises the steps of:

predicting a probability of a memory page hit on a next transaction; and

enabling RAS active mode if the probability of a page hit exceeds a predetermined level.

7. The method of claim 6 wherein the processor has an internal cache, and wherein the method further comprises tracking a ratio of bus cycles to bus cycles during memory accesses.

8. The method of claim 5 wherein the system has a plurality of levels of cache and wherein the method further comprises the steps of:

tracking a ratio of bus cycles to bus cycles during which a particular level of cache is accessed;

tracking a ratio of cache hits to cache misses for the particular cache level; and

setting the mode of the particular cache level operation based on the ratios.

9. The method of claim 5 wherein only a bank of the data cache containing the information is enabled responsive to a cache hit.

10. In a computer system having a CPU coupled to a memory by a bus, an apparatus for optimizing characteristics of a memory subsystem comprising:

means for recording behavior of the subsystem; and

means for dynamically enabling portions of the memory subsystem in response to the recorded behavior wherein a tag cache is enabled if the recorded behavior indicates a first probability of an event, a data cache is enabled if the recorded behavior indicates a second probability of the event and the data cache is only enabled if the event occurs if the recorded behavior does not indicate the second probability of the event.

11. The apparatus of claim 10 wherein the means for recording comprises:

means for tracking the ratio of bus cycles to bus cycles during which a portion of the memory subsystem is accessed.

12. The apparatus of claim 10 wherein the means for recording comprises first means for predicting a probability of a cache hit;

and wherein the means for dynamically enabling comprises means for dynamically setting a mode of cache operation responsive to the predicting means.

13. The apparatus of claim 12 wherein the means for dynamically enabling further comprises:

second means for predicting a probability of a page hit in main memory; and

means for dynamically setting a mode of main memory operation responsive to the predicting means, second predicting means, and the tracking means.

14. The apparatus of claim 13 wherein the first and second predicting means comprise up-down counters coupled to comparators.

15. The apparatus of claim 12 wherein the dynamically setting means further comprises

first means for enabling the tag cache;

and

second means for enabling the data cache.

16. The apparatus of claim 15 wherein the second enabling means can independently enable individual data arrays within the data cache.