Memory buffer system using a single pointer to reference multiple associated data

• US 5,860,149 A
• Filed: 06/07/1995
• Issued: 01/12/1999
• Est. Priority Date: 06/07/1995
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Emulex Corporation (Broadcom, Inc.)
• Inventors: Chau, Vi, Fiacco, Peter, Rickard, Wayne
• Primary Examiner(s): Lim, Krisna
• Application Number:
  US08/484,592
• Time in Patent Office: 1,315 Days
• Field of Search: 395/456, 395/419, 711/209, 711/212, 711/129
• US Class Current: 711/209
• CPC Class Codes: G06F 12/023 Free address space management
• CPC Class Codes: G06F 2205/064 Linked list, i.e. structure using pointers, e.g. allowing non-contiguous address segments in one logical buffer or dynamic buffer space allocation
• CPC Class Codes: G06F 5/06 for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor G06F7/78 takes precedence

Abstract

A partitioned memory is divided into a number of large buffers, and one or more of the large buffers is divided to create an equal number of small buffers. Each remaining large buffer is associated with one small buffer, and the paired buffers may be addressed by a single pointer. The pointers are stored in a first-in-first-out unit to create a pool of available buffer pairs.

Claims

1. A method of partitioning a buffer memory, comprising:

(a) dividing the buffer memory into a first number of large blocks;

(b) dividing at least one of the large blocks into a second number of small blocks;

(c) associating each remaining large block with at least one small block as a linked buffer pair; and

(d) addressing each linked pair of associated large and small blocks with a single pointer.

2. The method of claim 1 wherein the first number equals the second number.

3. The method of claim 2 wherein each remaining large buffer is associated with a single small buffer.

4. The method of claim 3, further comprising shifting a portion of the pointer to alternate between the small buffer and the large buffer.

5. The method of claim 3 wherein each of the large buffers contains an equal number of bytes and each of the small buffers contains an equal number of bytes.

6. The method of claim 2 wherein the first number is an integer multiple of 64.

7. A method of partitioning a buffer memory, comprising:

(a) dividing the buffer memory into a plurality of large blocks;

(b) dividing at least one of the large blocks into a plurality of small blocks;

(c) associating each remaining large block with at least one small block as a linked buffer pair; and

(d) addressing each linked pair of associated large and small blocks with a single pointer.

8. A method of partitioning a memory, comprising:

(a) dividing the memory into a first number of large buffers;

(b) dividing one of the large buffers into a second number of small buffers;

(c) associating each remaining large buffer in the memory with at least one small buffer in the memory as a linked buffer pair; and

(d) addressing each linked pair of associated large and small buffers with a single pointer.

9. The method of claim 8 wherein exactly one of the large buffers is divided into a second number of small buffers.

10. The method of claim 9 wherein the first number equals the second number.

11. The method of claim 8 further comprising adding a new memory module to the memory and partitioning the new memory module in the same manner as the previous memory.

12. An apparatus for storing data comprising:

(a) a memory divided into a first number of large blocks, at least one of the large blocks divided into a second number of small blocks, each remaining large block associated with at least one small block as a linked buffer pair; and

(b) a plurality of buffer pointers, each linked pair of associated large and small blocks addressed by a single buffer pointer.

13. The apparatus of claim 12 wherein the first number equals the second number.

14. The apparatus of claim 13 wherein the memory address of the small buffer constitutes a shift of a portion of the memory address of the large buffer.

15. The apparatus of claim 13 wherein each of the large buffers contains an equal number of bytes and each of the small buffers contains an equal number of bytes.