High-frequency wireless communication system on a single ultrathin silicon on sapphire chip

• US 5,861,336 A
• Filed: 11/30/1995
• Issued: 01/19/1999
• Est. Priority Date: 07/12/1993
• Status: Expired due to Term

• Current Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Burgener, Mark L., Reedy, Ronald E.
• Primary Examiner(s): DANG, TRUNG Q
• Application Number:
  US08/565,682
• Time in Patent Office: 1,146 Days
• Field of Search: 437/21, 437/25, 437/26, 437/84, 437/62, 437/63, 437/977, 148/DIG. 150, 438/407, 438/413, 438/486, 438/517, 438/526, 438/530, 438/977
• US Class Current: 438/407
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02694 Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76281 Lateral isolation by selective oxidation of silicon
• CPC Class Codes: H01L 21/86 the insulating body being sapphire, e.g. silicon on sapphire structure, i.e. SOS
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78657 SOS transistors
• CPC Class Codes: H10B 10/15 comprising a resistor load element
• CPC Class Codes: Y10S 148/15 Silicon on sapphire SOS
• CPC Class Codes: Y10S 438/967 Semiconductor on specified insulator
• CPC Class Codes: Y10S 438/974 Substrate surface preparation
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A high-frequency wireless communication system on a single ultrathin silicon on sapphire chip is presented. This system incorporates analog, digital (logic and memory) and high radio frequency circuits on a single ultrathin silicon on sapphire chip. The devices are fabricated using conventional bulk silicon CMOS processing techniques. Advantages include single chip architecture, superior high frequency performance, low power consumption and cost effective fabrication.

Claims

1. A method of fabricating a semiconductor substrate structure comprising the steps of:

(a) forming a substantially monocrystalline silicon layer on an electrically insulating substrate;

(b) implanting ions in the silicon layer to amorphorize an inner portion of the silicon layer adjacent to the substrate while maintaining an outer portion of the silicon layer substantially monocrystalline;

(c) annealing the silicon layer in an inert ambient for causing solid phase epitaxial regrowth of the inner portion from the outer portion by ramping a temperature of the silicon layer upwardly from an initial value; and

(d) displacing the inert ambient with an oxidizing ambient and exposing the silicon layer to the oxidizing ambient for surface oxidation thereof when the temperature of the silicon layer reaches a first predetermined value, thereby forming a first surface layer of oxidized silicon, and subsequently increasing the temperature of the silicon layer to a second predetermined value.

2. A method as defined in claim 1 further comprising the step of:

(e) removing the first surface layer of oxidized silicon by etching.

3. A method as defined in claim 2 further comprising the steps of:

(f) oxidizing the silicon layer a second time to form a second surface layer of oxidized silicon; and

(g) removing the second surface layer of oxidized silicon by etching.

4. A method of fabricating a semiconductor substrate structure comprising the steps of:

(a) forming a substantially monocrystalline silicon layer on a surface of an electrically insulating substrate;

(b) implanting ions in the silicon layer to form an amorphous region in the silicon layer near the surface of the insulating substrate while leaving substantially monocrystalline silicon in another region of the silicon layer which is adjacent to the amorphous region;

(c) annealing the silicon layer in an inert ambient to cause solid phase epitaxial regrowth of the amorphous region;

(d) displacing the inert ambient with an oxidizing ambient and exposing the silicon layer to the oxidizing ambient for surface oxidation thereof thereby forming a first surface layer of oxidized silicon;

(e) removing the first surface layer of oxidized silicon by etching;

(f) oxidizing the silicon layer a second time to form a second surface layer of oxidized silicon; and

(g) removing the second surface layer of oxidized silicon by etching.

5. A method of fabricating a silicon on sapphire wafer having an intrinsic silicon layer on a sapphire substrate, said method comprising the steps of:

epitaxially depositing a layer of silicon on a surface of a sapphire substrate;

implanting a given ion species into said layer of silicon under such conditions that said implanted ions form a buried amorphous region in said silicon layer which extends substantially from said surface of said sapphire substrate into said layer of silicon, thus leaving a surface layer of monocrystalline silicon covering said buried amorphous region;

maintaining said layer of silicon at or below a temperature of approximately zero degrees centigrade (0°

C.) such that said temperature is substantially uniform throughout said layer of silicon during said ion implanting step;

annealing the wafer to induce solid phase epitaxial regrowth of said buried amorphous region using said surface layer of monocrystalline silicon as a crystallization seed;

oxidizing said layer of silicon by exposure to an oxidizing ambient for surface oxidation thereof thereby forming a first surface layer of oxidized silicon;

removing said first surface layer of oxidized silicon;

oxidizing said layer of silicon a second time to form a second surface layer of oxidized silicon; and

removing said second surface layer of oxidized silicon.

6. A method as defined in claim 5 wherein said implanting step further comprises the step of selecting the energy and intensity of said implanting ions from within a range of energy and intensity values having a lower limit which is sufficient to amorphize said buried region of silicon and an upper limit which is insufficient to release substrate-originated contaminants into said silicon layer.

7. A method as defined in claim 5 further comprising the step of performing a high temperature anneal sequence at or below approximately 950°

C. in a non-oxidizing environment thereby removing residual defects in said layer of silicon without introducing bandgap or interface states.

8. A method as defined in claim 7 wherein said step of performing a high temperature anneal sequence in a non-oxidizing environment to remove residual defects in said layer of silicon without introducing bandgap or interface states further comprises selecting the temperature of said high temperature anneal to be within the range of from approximately 900°

C. to approximately 950°

C.

9. A method as defined in claim 5 further comprising the step of controlling said steps of oxidizing and removing to reduce said layer of silicon on said sapphire substrate to a thickness which is in the range of from approximately 50 nm to approximately 110 nm.

10. A method as defined in claim 5 wherein said step of annealing the wafer to induce solid phase epitaxial regrowth of said buried amorphous region further comprises selecting the temperature of said annealing step to be within the range of from approximately 500°

C. to approximately 600°

C.

11. A method as defined in claim 5 wherein said step of implanting a given ion species into said layer of silicon further comprises the steps of:

selecting silicon as said given ion species; and

selecting the energy and intensity of said silicon ions from within a range of energy and intensity values having a lower limit which is sufficient to amorphize said buried region of silicon and an upper limit which is insufficient to release substrate-originated contaminants into said silicon layer.

12. A method as defined in claim 11 wherein said step of selecting said silicon ion energy further comprises selecting said silicon ion energy to be within the range of from approximately 185 keV to approximately 200 keV.

13. A method as defined in claim 11 wherein said step of selecting said silicon ion intensity further comprises selecting said silicon ion intensity to be within the range of from approximately 5×

10¹⁴ cm^-2 to approximately 7×

10¹⁴ cm^-2.

14. A method as defined in claim 5 wherein said step of maintaining said layer of silicon at or below a temperature of approximately zero degrees centigrade (0°

C.) which is substantially uniform throughout said layer of silicon during said ion implanting step further comprises flooding a surface of said sapphire substrate which does not have said layer of silicon deposited thereon with a cooled gas.

15. A method as defined in claim 5 wherein said step of epitaxially depositing a layer of silicon on a surface of a sapphire substrate further comprises controlling the deposition to produce a silicon layer having a thickness in the range of from approximately 250 nm to approximately 270 nm.

16. A method of fabricating a silicon on sapphire wafer having an intrinsic silicon layer on a sapphire substrate, said method comprising the steps of:

epitaxially depositing a layer of silicon on a surface of a sapphire substrate;

positioning said sapphire substrate adjacent a chamber through which flows a coolant such that said coolant contacts said sapphire substrate;

implanting a given ion species into said layer of silicon under such conditions that said implanted ions form a buried amorphous region in said silicon layer which extends substantially from said surface of said sapphire substrate into said layer of silicon, thus leaving a surface layer of monocrystalline silicon covering said buried amorphous region;

controlling the flow rate or the temperature or both the flow rate and the temperature of said coolant through said chamber to maintain said layer of silicon substantially at or below a temperature of approximately zero degrees centigrade (0°

C.) during said ion implanting step;

annealing the wafer to induce solid phase epitaxial regrowth of said buried amorphous region using said surface layer of monocrystalline silicon as a crystallization seed;

oxidizing said silicon layer by exposure to an oxidizing ambient for surface oxidation thereof thereby forming a first surface layer of oxidized silicon;

removing said first surface layer of oxidized silicon;

oxidizing said silicon layer a second time to form a second surface layer of oxidized silicon; and

removing said second surface layer of oxidized silicon.

17. A method as defined in claim 16 further comprising the step of flowing a gaseous coolant through said chamber.

18. A method as defined in claim 17 further comprising the step of selecting nitrogen as said gaseous coolant.