Hierarchically connectable configurable cellular array

• US 5,861,761 A
• Filed: 10/03/1996
• Issued: 01/19/1999
• Est. Priority Date: 11/05/1992
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Kean, Thomas A.
• Primary Examiner(s): SANTAMAURO, JON P
• Application Number:
  US08/725,173
• Time in Patent Office: 838 Days
• Field of Search: 326/38-41, 326/47
• US Class Current: 326/41
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17752 for hot reconfiguration
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration
• CPC Class Codes: H03K 19/17758 for speeding up configuration or reconfiguration

Abstract

An field programmable gate array (FPGA) of cells arranged in rows and columns is interconnected by a hierarchical routing structure. Switches separate the cells into blocks and into blocks of blocks with routing lines interconnecting the switches to form the hierarchy. Also, select units for allowing memory bits to be addressed both individually and in large and arbitrary groups are disclosed. Further a control store for configuring the FPGA is addressed as an SAME and can be dynamically reconfigured during operation.

Claims

1. A hierarchically-structured programmable logic array, comprising:

a plurality of sectors, each sector comprising;

a plurality of logic cells; and

a sector bus system for interconnecting said logic cells within said sector;

a block bus system disposed externally to said sectors; and

an interface for selectively coupling the plurality of sector bus systems to said block bus system, said interface including a K number of lower level switches coupled to said sector bus systems, and an N number of higher level switches coupled to said block bus system, where N is less than K.

2. The programmable logic array of claim 1, wherein said interface comprises:

a multiplexer including a plurality of multiplexed ports coupled to at least one of said sector bus systems,

a de-multiplexed port; and

a second port coupled to said block bus system.

3. The programmable logic array of claim 1, wherein at least one of said sectors comprises:

said plurality of logic cells arranged in rows and columns;

a sector bus system comprising;

at least one sector row bus disposed between two rows of said logic cells, and coupled to the logic cells of one of said two rows; and

at least one sector column bus disposed between two columns of said logic cells, and coupled to the logic cells of one of said two columns; and

means for selectively coupling at least a portion of said sector row bus to at least a portion of said sector column bus.

4. A hierarchically-structured programmable logic array, comprising:

a plurality of sectors arranged in rows and columns, each sector comprising;

a plurality of logic cells; and

a sector bus system for interconnecting said logic cells within said sector;

a block bus system including at least one block row bus disposed between two rows of said sectors, and at least one block column bus disposed between two columns of said sectors;

means for selectively coupling at least a portion of said block row bus to at least a portion of said block column bus; and

an interface for selectively coupling the plurality of sector bus systems to said block bus system, said interface including a K number of lower level switches coupled to said sector bus systems, and an N number of higher level switches coupled to said block bus system, where N is less than K.

5. The programmable logic array of claim 4, wherein said interface comprises:

a multiplexer including a plurality of multiplexed ports coupled to at least one of said sector bus systems,

a de-multiplexed port; and

a second port selectively coupled to said block bus system.

6. The programmable logic array of claim 4, wherein at least one of said sectors comprises:

said plurality of logic cells arranged in rows and columns;

a sector bus system comprising;

at least one sector row bus disposed between two rows of said logic cells, and coupled to the logic cells of one of said two rows; and

at least one sector column bus disposed between two columns of said logic cells, and coupled to the logic cells of one of said two columns; and

means for selectively coupling at least a portion of said sector row bus to at least a portion of said sector column bus.

7. A hierarchically-structured programmable logic array, comprising:

(a) a plurality of blocks, wherein at least one of said plurality of blocks comprises;

(a)(1) a plurality of sectors arranged in rows and columns, each sector comprising;

(a)(1)(i) a plurality of logic cells; and

(a)(1)(ii) a sector bus system for interconnecting said logic cells within said sector;

(a)(2) a block bus system, comprising;

(a)(2)(i) at least one block row bus disposed between two rows of said plurality of sectors, and accessible to at least one of the sectors in said two rows; and

(a)(2)(ii) at least one block column bus disposed between two columns of said plurality of sectors, and accessible to at least one of the sectors in said two columns;

(a)(3) means for coupling at least a portion of said block row bus to at least a portion of said block column bus; and

(a)(4) a sector interface for selectively coupling the plurality of sector bus systems to said block bus system;

(b) a chip bus system disposed external to said blocks; and

(c) a block interface for selectively coupling said blocks to said chip bus system.

8. The programmable logic array of claim 7, wherein said sector interface includes a K number of lower level switches coupled to said sector bus systems, and an N number of higher level switches coupled to said block bus system, where N is less than K.

9. The programmable logic array of claim 7, wherein said block interface includes a K number of lower level switches coupled to said block bus systems, and an N number of higher level switches coupled to said chip bus system, where N is less than K.

10. The programmable logic array of claim 7, wherein at least one of said sectors comprises:

said plurality of logic cells arranged in rows and columns;

a sector bus system comprising;

at least one sector row bus disposed between two rows of said logic cells, and coupled to the logic cells of one of said two rows; and

at least one sector column bus disposed between two columns of said logic cells, and coupled to the logic cells of one of said two columns; and

means for selectively coupling at least a portion of said sector row bus to at least a portion of said sector column bus.

11. The programmable logic array of claim 10, wherein said sector interface includes a K number of lower level switches coupled to said sector bus systems, and an N number of higher level switches coupled to said block bus system, where N is less than K.

12. The programmable logic array of claim 10, wherein said block interface includes a K number of lower level switches coupled to said block bus systems, and an N number of higher level switches coupled to said chip bus system, where N is less than K.

13. A hierarchically-structured programmable logic array, comprising:

(a) a plurality of blocks, wherein at least one of said plurality of blocks comprises;

(a)(1) a plurality of sectors, each sector comprising;

(a)(1)(i) a plurality of logic cells arranged in rows and columns; and

(a)(1)(ii) a sector bus system comprising;

(a)(1)(ii)(A) at least one sector row bus disposed between two rows of said logic cells, and coupled to the logic cells of one of said two rows; and

(a)(1)(ii)(B) at least one sector column bus disposed between two columns of said logic cells, and coupled to the logic cells of one of said two columns; and

(a)(1)(ii)(C) means for selectively coupling at least a portion of said sector row bus to at least a portion of said sector column bus

(a)(2) a block bus system; and

(a)(3) a sector interface for selectively coupling the plurality of sector bus systems to said block bus system;

(b) a chip bus system disposed external to said blocks; and

(c) a block interface for selectively coupling said blocks to said chip bus system.

14. The programmable logic array of claim 13, wherein said sector interface includes a K number of lower level switches coupled to said sector bus systems, and an N number of higher level switches coupled to said block bus systems, where N is less than K.

15. The programmable logic array of claim 13, wherein said block interface includes a K number of lower level switches coupled to said block bus systems, and an N number of higher level switches coupled to said chip bus system, where N is less than K.

16. A hierarchically-structured programmable logic array, comprising:

a plurality of blocks arranged in rows and columns;

a chip bus system comprising;

at least one chip row bus disposed between two rows of said plurality of blocks and accessible to at least one of the blocks in said two rows; and

at least one chip column bus disposed between two columns of said plurality of blocks and accessible to at least one of the blocks in said two columns;

means for coupling at least a portion of said chip row bus to at least a portion of said chip column bus; and

a block interface for selectively coupling said blocks to said chip bus system;

wherein each of said plurality of blocks comprises;

a plurality of sectors, each sector comprising;

a plurality of logic cells; and

a sector bus system for interconnecting said

logic cells within said each sector;

a block bus system disposed external to said sectors, said block bus system selectively coupled to said block interface; and

a sector interface for selectively coupling the plurality of sector bus systems to said block bus system.

17. The programmable logic array of claim 16, wherein said sector interface includes a K number of lower level switches coupled to said sector bus systems, and an N number of higher level switches coupled to said block bus system, where N is less than K.

18. The programmable logic array of claim 16, wherein said block interface includes a K number of lower level switches coupled to said block bus systems, and an N number of higher level switches coupled to said chip bus system, where N is less than K.

19. The programmable logic array of claim 16, wherein at least one of said sectors comprises:

said plurality of logic cells arranged in rows and columns;

a sector bus system comprising;

at least one sector row bus disposed between two rows of said logic cells, and coupled to the logic cells of one of said two rows; and

at least one sector column bus disposed between two columns of said logic cells, and coupled to the logic cells of one of said two columns; and

means for selectively coupling at least a portion of said sector row bus to at least a portion of said sector column bus.

20. The programmable logic array of claim 19, wherein said sector interface includes a K number of lower level switches coupled to said sector bus systems, and an N number of higher level switches coupled to said block bus system, where N is less than K.

21. The programmable logic array of claim 19, wherein said block interface includes a K number of lower level switches coupled to said block bus systems, and an N number of higher level switches coupled to said chip bus system, where N is less than K.

22. The programmable logic array of claim 16, wherein at least one of said blocks comprises:

a plurality of sectors arranged in rows and columns, each sector comprising;

a plurality of logic cells; and

a sector bus system for interconnecting said logic cells within said each sector;

a block bus system, coupled selectively to said block interface, comprising;

at least one block row bus disposed between two rows of said sectors; and

at least one block column bus disposed between two columns of said sectors; and

means for coupling at least a portion of said block row bus to at least a portion of said block column bus.

23. The programmable logic array of claim 22, wherein said sector interface includes a K number of lower level switches coupled to said sector bus systems, and an N number of higher level switches coupled to said block bus systems, where N is less than K.

24. The programmable logic array of claim 22, wherein said block interface includes a K number of lower level switches coupled to said block bus systems, and an N number of higher level switches coupled to said chip bus system, where N is less than K.

25. The programmable logic array of claim 22, wherein at least one of said sectors comprises:

said plurality of logic cells arranged in rows and columns;

a sector bus system comprising;

at least one sector row bus disposed between two rows of said logic cells, and coupled to the logic cells of one of said two rows; and

at least one sector column bus disposed between two columns of said logic cells, and coupled to the logic cells of one of said two columns; and

means for selectively coupling at least a portion of said sector row bus to at least a portion of said sector column bus.

26. The programmable logic array of claim 25, wherein said sector interface includes a K number of lower level switches coupled to said sector bus systems, and an N number of higher level switches coupled to said block bus systems, where N is less than K.

27. The programmable logic array of claim 25, wherein said block interface includes a K number of lower level switches coupled to said block bus systems, and an N number of higher level switches coupled to said chip bus system, where N is less than K.