Digital to analog converter and dynamic current mirror structure to simplify on-chip wave shaping

• US 5,861,830 A
• Filed: 07/25/1997
• Issued: 01/19/1999
• Est. Priority Date: 02/12/1996
• Status: Expired due to Term

• Current Assignee: RPX Corporation
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Cheng, Yi, Runaldue, Thomas Jefferson
• Primary Examiner(s): YOUNG, BRIAN K
• Application Number:
  US08/900,954
• Time in Patent Office: 543 Days
• Field of Search: 341/135, 341/143, 341/145, 341/147
• US Class Current: 341/135
• CPC Class Codes: H03M 1/662 Multiplexed conversion systems
• CPC Class Codes: H03M 1/745 with weighted currents
• CPC Class Codes: H03M 1/747 with equal currents which are switched by unary decoded digital signals

Abstract

A digital to analog converter that includes circuitry that converts sequences of positive and negative digital data samples into electrical currents and current mirror circuitry that generates an analog waveform by combining and amplifying the electrical currents.

Claims

1. A digital to analog conversion circuit, comprising:

circuitry for converting a sequence of positive digital data samples into a first electrical current and for converting a sequence of negative digital data samples into a second electrical current;

current mirror circuitry that generates an analog waveform by combining and amplifying the first and second electrical currents, wherein said current mirror circuitry includes;

a current amplifying circuit; and

a common mode adjustment circuit.

2. The circuit of claim 1, wherein said current amplifying circuit includes:

a first amplifying current mirror circuit coupled to amplify said first electrical current;

a second amplifying current mirror circuit coupled to amplify said second electrical current.

3. The circuit of claim 2, wherein said common mode adjustment circuit includes:

a first transconductance amplifier coupled to said first amplifying current mirror; and

a second transconductance amplifier coupled to said second amplifying current mirror.

4. The circuit of claim 3, wherein:

said current amplifying circuit further includes a third amplifying current mirror circuit coupled to amplify said first electrical current and a fourth amplifying current mirror circuit coupled to amplify said second electrical current; and

said common mode adjustment circuit further includes a third transconductance amplifier coupled to said third amplifying current mirror and a fourth transconductance amplifier coupled to said fourth amplifying current mirror.

5. The circuit of claim 2, wherein circuitry for converting includes:

a first plurality of transistors coupled to be turned on and off by said sequence of positive digital data samples;

a first plurality of supply current mirror circuits, where each supply current mirror circuit in said first plurality of supply current mirror circuits is coupled to a respective one of said transistors in said first plurality of transistors, and wherein each supply current mirror circuit in said first plurality of supply current mirror circuits is coupled to duplicate a supply current;

a second plurality of transistors coupled to be turned on and off by said sequence of negative digital data samples; and

a second plurality of supply current mirror circuits, where each supply current mirror circuit in said second plurality of supply current mirror circuits is coupled to a respective one of said transistors in said second plurality of transistors, and wherein each supply current mirror circuit in said second plurality of supply current mirror circuits is coupled to duplicate said supply current.

6. A digital to analog conversion circuit comprising:

a digital-to-analog converter, said digital-to-analog converter coupled to receive a sequence of positive digital data samples and to generate on a first output a first electrical current representative of said sequence of positive digital data samples, said digital-to-analog converter further coupled to receive a sequence of negative digital data samples and to generate on a second output a second electrical current representative of said sequence of negative digital data samples; and

a current mirror circuit coupled to said digital-to-analog converter, said current mirror circuit including a current amplifying circuit and a common mode adjustment circuit, said current mirror circuit to generate on a current mirror circuit output an analog waveform by combining and amplifying the first and second electrical currents.

7. The digital to analog conversion circuit of claim 6, wherein:

said current amplifying circuit includes a first amplifying current mirror circuit coupled to amplify said first electrical current, a second amplifying current mirror circuit coupled to amplify said second electrical current, a third amplifying current mirror circuit coupled to amplify said first electrical current and a fourth amplifying current mirror circuit coupled to amplify said second electrical current;

said common mode adjustment circuit includes a first transconductance amplifier coupled to said first amplifying current mirror, a second transconductance amplifier coupled to said second amplifying current mirror, a third transconductance amplifier coupled to said third amplifying current mirror and a fourth transconductance amplifier coupled to said fourth amplifying current mirror.

8. The circuit of claim 7, wherein said digital-to-analog converter includes:

a first plurality of transistors coupled to be turned on and off by said sequence of positive digital data samples;

a first plurality of supply current mirror circuits, where each supply current mirror circuit in said first plurality of supply current mirror circuits is coupled to a respective one of said transistors in said first plurality of transistors, and wherein each supply current mirror circuit in said first plurality of supply current mirror circuit is coupled to duplicate a supply current;

a second plurality of transistors coupled to be turned on and off by said sequence of negative digital data samples; and

a second plurality of supply current mirror circuits, where each supply current mirror circuit in said second plurality of supply current mirror circuits is coupled to a respective one of said transistors in said second plurality of transistors, and wherein each supply current mirror circuit in said first plurality of supply current mirror circuits is coupled to duplicate said supply current.