Buffer manager

• US 5,861,894 A
• Filed: 06/07/1995
• Issued: 01/19/1999
• Est. Priority Date: 06/24/1993
• Status: Expired due to Term

• Current Assignee: Chartoleaux KG LLC (Intellectual Ventures LLC)
• Original Assignee: Discovision Associates (Pioneer Corporation)
• Inventors: Finch, Helen R., Sotheran, Martin William
• Primary Examiner(s): Hjerpe, Richard A.
• Assistant Examiner(s): CHANG, KENT WU
• Application Number:
  US08/474,603
• Time in Patent Office: 1,322 Days
• Field of Search: 345/200, 345/190, 345/193, 345/202, 345/196, 345/516, 345/515
• US Class Current: 345/573
• CPC Class Codes: G09G 5/00 Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators image data processing or generation, in general G06T
• CPC Class Codes: H04N 21/44004 involving video buffer management, e.g. video decoder buffer or video display buffer
• CPC Class Codes: H04N 9/8042 involving data reduction

Abstract

This invention provides a method to control the buffering of encoded video data organized as frames or fields. This method involves determining the picture number of each incoming decoded frame, determining the expected presentation number at any time and marking any buffer as ready when its picture number is on or after the presentation number.

Claims

1. An image formatter for processing encoded video data comprising:

an input element for receiving encoded data having a frame rate and an arrival rate;

a memory defining at least three buffers for storage of the encoded data, one of said buffers being a display buffer, and another of said buffers being an arrival buffer;

a write address generator for generating write addresses for data being stored thereat in said memory;

a read address generator for generating read addresses for reading data stored there at in said memory;

an output interface linked to said read address generator that produces decoded data at a display rate; and

a buffer manager responsive to said arrival rate, said display rate, and said frame rate for allocating said buffers to said write address generator and said read address generator, wherein said buffers are allocated to said write address generator in response to a timing regime.

2. The image formatter according to claim 1, wherein said read address generator and said buffer manager are connected by a plurality of two-wire interfaces, wherein said two-wire interfaces each comprise:

a sender, a receiver, and a clock connected to said sender and said receiver, wherein data is transferred from said sender to said receiver upon a transition of said clock only when said sender is ready and said receiver is ready.

3. The image formatter according to claim 1, wherein said input element and said buffer manager are connected by a two-wire interface, wherein said two-wire interface comprises:

a sender, a receiver, and a clock connected to said sender and said receiver, wherein data is transferred from said sender to said receiver upon a transition of said clock only when said sender is ready and said receiver is ready.

4. The image formatter according to claim 1, wherein said write address generator and said buffer manager are connected by a two-wire interface, wherein said two-wire interface comprises:

a sender, a receiver, and a clock connected to said sender and said receiver, wherein data is transferred from said sender to said receiver upon a transition of said clock only when said sender is ready and said receiver is ready.

5. The image formatter according to claim 1, further comprising a setup register having a picture index stored therein, wherein said buffer manager asserts a first signal when received encoded data represents a picture having an index corresponding to said picture index, and wherein said buffer manager asserts a second signal when said display buffer has a picture number that is less than a current presentation number.

6. The image formatter according to claim 1, wherein said timing regime comprises an arrival rate of video data.

7. The image formatter according to claim 1, wherein said timing regime comprises an display rate of video data.

8. The image formatter according to claim 1, wherein said timing regime comprises an presentation rate of an encoded video sequence.