Information processing system

• US 5,862,083 A
• Filed: 04/30/1996
• Issued: 01/19/1999
• Est. Priority Date: 04/08/1993
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi Keiyo Engineering Company Limited, Hitachi, Ltd., Hitachi ULSI Engineering Corp
• Inventors: Saito, Manabu, Kikuchi, Takashi, Katayama, Kunihiro, Suzuki, Takeshi, Wada, Takeshi, Yamagami, Hajime, Totsuka, Takashi, Kaki, Kenichi, Tsunehiro, Takashi, Kitahara, Jun, Hattori, Ryuichi, Tobita, Tsunehiro, Seki, Yukihiro, Okubo, Takao, Takaya, Yosio, Kadowaki, Shigeru, Kishi, Masamichi
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US08/640,998
• Time in Patent Office: 994 Days
• Field of Search: 365/185.01, 365/189.07, 365/185.09, 365/185.11, 365/185.22, 365/230.01, 365/230.03
• US Class Current: 365/185.09
• CPC Class Codes: G06F 11/1433 during software upgrading
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/312 In storage controller
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/068 Hybrid storage device
• CPC Class Codes: G11C 29/765 in solid state disks
• CPC Class Codes: G11C 29/789 using non-volatile cells or latches
• CPC Class Codes: G11C 29/82 for EEPROMs

Abstract

A control method and system when a flash memory is used as a semiconductor disk or a main memory in an information processing system. A semiconductor file system comprises a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller which controls the memories, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating the correspondence between physical addresses at which the data is stored and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information required for inputting and outputting the data from and to the external system and read-only data of the data. The controller comprises control means for determining a physical sector address forming predetermined high-order bits of the physical address when data is output from the first nonvolatile memory or when data is input to the volatile memory, means for storing the determined physical sector address, and means for consecutively generating addresses in a sector determined by the physical sector address.

Claims

1. An information processing system comprising

a central processing unit,

input means for inputting data,

output means for outputting data,

volatile storage means for storing data,

nonvolatile storage means being capable of electrically rewriting stored data to which an address space accessible by said central processing unit is allocated,

data control means for at least transferring data between said volatile storage means and said nonvolatile storage means,

means for registering addresses of data stored in said volatile storage means in said nonvolatile storage means, and

means for comparing the addresses registered in said address registration means with an address output by said central processing unit to make a data access,

wherein when the address output by said central processing unit to make a data access is input to said address comparison means and said address comparison means makes a comparison therebetween and outputs a comparison result, said data control means determines whether or not the address is one of the addresses registered in said address registration means in response to the comparison result, and when the address is one of the registered addresses, accesses the registered address in said volatile storage means;

in contrast, when the address is not any of the registered addresses, newly registers at least a predetermined range of addresses containing the address in said address registration means, creates a new data storage area corresponding to the newly registered addresses in said volatile storage means, and accesses at least one of the newly registered addresses.

2. An information processing system as claimed in claim 1 further comprising access history record means for recording access history information.

3. An information processing system as claimed in claim 2 wherein when said volatile storage means fills with data and does not contain any new data storage area, said data control means references the access history information in said access history record means for detecting an address the last access to which is the oldest among recorded addresses and deletes the address from said address registration means.

4. An information processing system as claimed in claim 3 wherein said data control means further transfers data in said volatile storage means corresponding to the address deleted from said address registration means to said nonvolatile storage means.

5. An information processing system as claimed in claim 1 wherein said volatile storage means is made of a ferroelectric random access memory (FRAM).

6. An information processing system as claimed in claim 1 further comprising power off means started by a power off operation when a power supply given to said system is turned off, save process means responsive to a power off process by said power off means for storing information including contents of internal registers contained in said information processing system and contents of internal registers contained in said input means and output means in some area of said nonvolatile storage means, and means for stopping the power supply to said system upon completion of the process of said save process means.

7. An information processing system as claimed in claim 1 wherein said data control means further monitors an amount of data stored in said volatile storage means and always reserves a data unstored area having a capacity equal to or greater than a predetermined capacity.

8. An information processing system as claimed in claim 1 further comprising write inhibit information storage means in which a write inhibit flag can be set indicating that a data write is inhibited for each of blocks into which said nonvolatile storage means is divided,

wherein when data is stored in one block of said nonvolatile storage means, if the write inhibit flag is provided corresponding to the block, said data control means outputs a message to the effect that a write request into said block is made to said output means.

9. An information processing system as claimed in claim 1 wherein said nonvolatile storage means is made of a flash memory.

10. An information processing system as claimed in claim 1 wherein if power of said information processing system is turned off, data in said address registration means is retained at least until power is again supplied to said information processing system.

11. An information processing system as claimed in claim 10 wherein when operation of said information processing system is restarted by supplying power again after a power supply to said information system is nonentarily stopped, the data retained in said address registration means is referenced and data stored in an area of said nonvolatile storage means that can be specified from the registered address data is transferred to and stored in an area of said volatile storage means that can be specified from a location in which said address registration means stores the address data, thereby restoring storage contents of said volatile storage means to a state when the power supply was nonentarily stopped.

12. An information processing system as claimed in claim 1 wherein when power of said information processing system is turned off, data in said address registration means is transferred to and stored in a specific location of said nonvolatile storage means for saving the data retained in said address registration means and when a power supply is started again, the saved data is restored in said address registration means, thereby preventing the data in said address registration means from being lost.

13. An information processing system as claimed in claim 1 wherein data stored in said volatile storage means by a write access from said central processing unit is written back into said nonvolatile storage means every given time period.

14. An information processing system as claimed in claim 13 wherein data in said address registration means is also saved in said nonvolatile storage means when the data stored in said volatile storage means is written back into said nonvolatile storage means every given period of time.

15. An information processing system as claimed in claim 1 wherein electrically rewritable nonvolatile storage means containing a serial buffer having a capacity of a plurality of bytes to input/output data from/to an external system is used as said nonvolatile storage means and wherein data of bytes less than the number of storage bytes of said serial buffer is transferred from said nonvolatile storage means to said volatile storage means and data of bytes equal to the number of storage bytes of said serial buffer is transferred from said volatile storage means to said nonvolatile storage means.