Method and apparatus for overriding bus prioritization scheme
First Claim
1. A bus arbiter circuit for a system including a bus and a plurality of devices which can request access to the bus at various times, each of the devices being configured to provide a bus request signal to the bus arbiter circuit when requesting access to the bus and to receive a bus grant signal from the bus arbiter circuit when granted access to the bus, the bus arbiter circuit comprising:
- circuitry for arbitrating access to the bus during an arbitration cycle in response to bus request signals from those of the plurality of devices requesting access, an outcome of the arbitration cycle being based on a corresponding priority level associated with each of the plurality of devices;
circuitry for granting access, via a respective bus grant signal, to one of those devices requesting access to the bus based on the outcome of the arbitration cycle;
circuitry for increasing the corresponding priority level associated with those of the plurality of devices which requested access to the bus but which were not granted access to the bus as a result of the arbitration cycle; and
circuitry for increasing the corresponding priority level of at least one of the plurality of devices above the priority level which would normally be assigned if the at least one of the plurality of devices requesting access to the bus was not granted access in response to receiving a hardware panic signal from the at least one of the plurality of devices indicative of the at least one of the plurality of devices desiring increased priority above the priority level which would normally be assigned.
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0 Petitions
Accused Products
Abstract
A bus arbiter circuit for a system including a bus and a plurality of devices which can request access to the bus at various times. The bus arbiter circuit includes circuitry for receiving requests for access to the bus from those of the plurality of devices desiring access to the bus during an arbitration cycle; circuitry for arbitrating access to the bus during the arbitration cycle in response to the received requests, an outcome of the arbitration cycle being based on a corresponding priority level associated with each of the plurality of devices; circuitry for granting access to one of those devices requesting access to the bus based on the outcome of the arbitration cycle; and circuitry for increasing the corresponding priority level associated with those of the plurality of devices which requested access to the bus but which were not granted access to the bus as a result of the arbitration cycle.
68 Citations
20 Claims
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1. A bus arbiter circuit for a system including a bus and a plurality of devices which can request access to the bus at various times, each of the devices being configured to provide a bus request signal to the bus arbiter circuit when requesting access to the bus and to receive a bus grant signal from the bus arbiter circuit when granted access to the bus, the bus arbiter circuit comprising:
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circuitry for arbitrating access to the bus during an arbitration cycle in response to bus request signals from those of the plurality of devices requesting access, an outcome of the arbitration cycle being based on a corresponding priority level associated with each of the plurality of devices; circuitry for granting access, via a respective bus grant signal, to one of those devices requesting access to the bus based on the outcome of the arbitration cycle; circuitry for increasing the corresponding priority level associated with those of the plurality of devices which requested access to the bus but which were not granted access to the bus as a result of the arbitration cycle; and circuitry for increasing the corresponding priority level of at least one of the plurality of devices above the priority level which would normally be assigned if the at least one of the plurality of devices requesting access to the bus was not granted access in response to receiving a hardware panic signal from the at least one of the plurality of devices indicative of the at least one of the plurality of devices desiring increased priority above the priority level which would normally be assigned. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A bus arbiter circuit for a system including a bus and a plurality of devices which can request access to the bus at various times, the bus arbiter circuit comprising:
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circuitry for receiving requests for access to the bus from those of the plurality of devices desiring access to the bus during an arbitration cycle; circuitry for arbitrating access to the bus during the arbitration cycle in response to the received requests, an outcome of the arbitration cycle being based on a corresponding priority level associated with each of the plurality of devices; circuitry for granting access to one of those devices requesting access to the bus based on the outcome of the arbitration cycle; circuitry for increasing the corresponding priority level associated with those of the plurality of devices which requested access to the bus but which were not granted access to the bus as a result of the arbitration cycle; and circuitry for increasing the corresponding priority level of at least one of the plurality of devices above the priority level which would normally be assigned if the at least one of the plurality of devices requesting access to the bus was not granted access in response to receiving a hardware panic signal from the at least one of the plurality of devices indicative of the at least one of the plurality of devices desiring increased priority above the priority level which would normally be assigned. - View Dependent Claims (11, 12, 13, 14)
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15. A method of bus arbitration in a system including a bus and a plurality of devices which can request access to the bus at various times, the method comprising the steps of:
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receiving requests for access to the bus from those of the plurality of devices desiring access to the bus during an arbitration cycle; arbitrating access to the bus during the arbitration cycle in response to the received requests, an outcome of the arbitration cycle being based on a corresponding priority level associated with each of the plurality of devices; granting access to one of those devices requesting access to the bus based on the outcome of the arbitration cycle; increasing the corresponding priority level associated with those of the plurality of devices which requested access to the bus but which were not granted access to the bus as a result of the arbitration cycle; and increasing the corresponding priority level associated with at least one of the plurality of devices above the priority level which would normally be assigned if the at least one of the plurality of devices requesting access to the bus was not granted access in response to receiving a hardware panic signal from the at least one of the plurality of devices indicative of the at least one of the plurality of devices desiring increased priority above the priority level which would normally be assigned. - View Dependent Claims (16, 17)
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18. A bus arbiter circuit for a system including a bus and a plurality of devices which can request access to the bus at various times, each of the devices being configured to provide a bus request signal to the bus arbiter circuit when requesting access to the bus and to receive a bus grant signal from the bus arbiter circuit when granted access to the bus, and at least one of the devices being configured to provide a hardware panic signal to the bus arbiter circuit indicative of the at least one device desiring increased priority, the bus arbiter circuit comprising:
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circuitry for arbitrating access to the bus during an arbitration cycle in response to bus request signals from those of the plurality of devices requesting access, an outcome of the arbitration cycle being based on a corresponding priority level associated with each of the plurality of devices; circuitry for granting access, via a respective bus grant signal, to one of those devices requesting access to the bus based on the outcome of the arbitration cycle; and circuitry for increasing the corresponding priority level associated with the at least one device above the priority level which would normally be assigned if the at least one device requesting access to the bus was not granted access in response to receiving the hardware panic signal from the at least one device indicative of the at least one device desiring increased priority above the priority level which would normally be assigned.
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19. A method of bus arbitration in a system including a bus and a plurality of devices which can request access to the bus at various times, the method comprising the steps of:
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receiving requests for access to the bus from those of the plurality of devices desiring access to the bus during an arbitration cycle; arbitrating access to the bus during the arbitration cycle in response to the received requests, an outcome of the arbitration cycle being based on a corresponding priority level associated with each of the plurality of devices; increasing the corresponding priority level associated with at least one of the plurality of devices above the priority level which would normally be assigned if the at least one of the plurality of devices requesting access to the bus was not granted access in response to receiving a hardware panic signal from the at least one of the plurality of devices indicative of the at least one of the plurality of devices desiring increased priority above the priority level which would normally be assigned; and granting access to one of those devices requesting access to the bus based on the outcome of the arbitration cycle. - View Dependent Claims (20)
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Specification