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Data transfer bus including divisional buses connectable by bus switch circuit

  • US 5,862,359 A
  • Filed: 12/03/1996
  • Issued: 01/19/1999
  • Est. Priority Date: 12/04/1995
  • Status: Expired due to Fees
First Claim
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1. A low power consumption data transfer bus comprising:

  • an LSI;

    a plurality of functional blocks within said LSI;

    a data transfer bus provided between said plurality of functional blocks;

    three or more divisional buses obtained by dividing said data transfer bus;

    a bus switch circuit for connecting said plurality of divisional buses to each other; and

    a decoder circuit for decoding an order signal which requires two of said plurality of divisional buses during an operation of said data transfer bus, and controlling said bus switch circuit so that only said two divisional buses are connected to each other in reply to a decode output,wherein said bus switch circuit is positioned in a predetermined section on a chip of said LSI and loads on said divisional buses are asymmetrical.

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