Data transfer bus including divisional buses connectable by bus switch circuit

• US 5,862,359 A
• Filed: 12/03/1996
• Issued: 01/19/1999
• Est. Priority Date: 12/04/1995
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Nozuyama, Yasuyuki
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Thlang, Eric S.
• Application Number:
  US08/758,580
• Time in Patent Office: 777 Days
• Field of Search: 395/280, 395/550, 395/800, 395/311, 395/307, 395/306, 395/308, 365/205, 364/200, 370/60
• US Class Current: 710/316
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In the low power consumption data transfer bus of the present invention, the mode of division of a bus is associated with a specific layout on an actual LSI chip or an actual LSI-mounted board, and access frequency between functional blocks connected to the bus and therefore the effect of the bus division can be obtained to the maximum degree for the object of achievement of the low power consumption. Further, the operation speed of the bus (that is, data transfer speed) can be improved as compared to the case where the bus is not divided. The data transfer bus includes a bus switch circuit connected so that one data transfer bus provided between a plurality of functional blocks within an LSI is divided into three or more divisional buses, and a decoder circuit for decoding an order signal which requires two of the plurality of divisional buses during an operation of the data transfer bus, and controlling the bus switch circuit so that only the two divisional buses are connected to each other in reply to a decode output.

Claims

1. A low power consumption data transfer bus comprising:

an LSI;

a plurality of functional blocks within said LSI;

a data transfer bus provided between said plurality of functional blocks;

three or more divisional buses obtained by dividing said data transfer bus;

a bus switch circuit for connecting said plurality of divisional buses to each other; and

a decoder circuit for decoding an order signal which requires two of said plurality of divisional buses during an operation of said data transfer bus, and controlling said bus switch circuit so that only said two divisional buses are connected to each other in reply to a decode output,

wherein said bus switch circuit is positioned in a predetermined section on a chip of said LSI and loads on said divisional buses are asymmetrical.

2. A low power consumption data transfer bus according to claim 1, wherein, of said plurality of functional blocks, a pair of functional blocks having a highest average access frequency with respect to the data transfer bus are connected to a divisional bus having a lightest load of said plurality of divisional buses.

3. A low power consumption data transfer bus according to claim 1, wherein said plurality of functional blocks are registered in the order of a data transfer time which is allowed to be shorter;

a maximum load which satisfies a predetermined data transfer time is obtained in both a case where data crosses the bus switch circuit, and a case where data does not cross the bus switch circuit;

a procedure that a pair of functional blocks having a highest average access frequency with respect to the data transfer bus, of said plurality of functional blocks, are connected to a divisional bus having a lightest load of said plurality of divisional buses, is executed; and

each time a functional block conforming to a condition of said data transfer time appears, said functional block is connected to a predetermined divisional bus prior to a functional block determined due to a power-saving requirement.

4. A low power consumption data transfer bus according to claim 1, wherein, of said plurality of functional blocks, a pair of functional blocks which require a shortest data transfer time are connected to a divisional bus having a lightest load of said plurality of divisional buses.

5. A low power consumption data transfer bus comprising:

an LSI;

a plurality of functional blocks within said LSI;

a data transfer bus provided between said plurality of functional blocks;

three or more divisional buses obtained by dividing said data transfer bus;

a bus switch circuit for connecting said plurality of divisional buses to each other;

a decoder circuit for decoding an order signal which requires two of said plurality of divisional buses during an operation of said data transfer bus, and controlling said bus switch circuit so that only said two divisional buses are connected to each other in reply to a decode output; and

a second bus switch circuit connected so that a part of said divisional buses is further divided into three or more divisional buses,

wherein said bus switch circuit and said second bus switch circuit are arranged to be away from each other in the chip of said LSI.

6. A low power consumption data transfer bus comprising:

a printed circuit board;

a plurality of LSIs mounted on said printed circuit board;

a data transfer bus provided between said plurality of LSIs;

a plurality of divisional buses obtained by dividing said data transfer bus;

a bus switch circuit for connecting said plurality of divisional buses to each other; and

a decoder circuit for decoding an order signal which requires two of said plurality of divisional buses during an operation of said data transfer bus, and controlling said bus switch circuit so that only said two divisional buses are connected to each other in reply to a decode output,

wherein said bus switch circuit is positioned in a predetermined section on said printed circuit board and loads on said divisional buses are asymmetrical.

7. A low power consumption data transfer bus according to claim 6, wherein, of said plurality of LSIs, a pair of LSIs having a highest average access frequency with respect to the data transfer bus are connected to a divisional bus having a lightest load of said plurality of divisional buses.

8. A low power consumption data transfer bus according to claim 6, wherein said plurality of LSIs are registered in the order of a data transfer time which is allowed to be shorter;

a maximum load which satisfies a predetermined data transfer time is obtained in both a case where data crosses the bus switch circuit, and a case where data does not cross the bus switch circuit;

a procedure that a pair of LSIs having a highest average access frequency with respect to the data transfer bus, of said plurality of LSIs, are connected to a divisional bus having a lightest load of said plurality of divisional buses, is executed; and

each time an LSI conforming to a condition of said data transfer time appears, said LSI is connected to a predetermined divisional bus prior to an LSI determined due to a power-saving requirement.

9. A low power consumption data transfer bus according to claim 6, wherein, of said plurality of LSIs, a pair of LSIs which require a shortest data transfer time are connected to a divisional bus having a lightest load of said plurality of divisional buses.

10. A low power consumption data transfer bus comprising:

a printed circuit board;

a plurality of LSIs mounted on said printed circuit board;

a data transfer bus provided between said plurality of LSIs;

a plurality of divisional buses obtained by dividing said data transfer bus;

a bus switch circuit for connecting said plurality of divisional buses to each other;

a decoder circuit for decoding an order signal which requires two of said plurality of divisional buses during an operation of said data transfer bus, and controlling said bus switch circuit so that only said two divisional buses are connected to each other in reply to a decode output; and

a second bus switch circuit connected so that a part of said divisional buses is further divided into three or more divisional buses,

wherein said bus switch circuit and said second bus switch circuit are arranged to be away from each other in the printed circuit board.