Electronic apparatus having a software controlled power switch

• US 5,862,394 A
• Filed: 03/21/1996
• Issued: 01/19/1999
• Est. Priority Date: 03/21/1996
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Jergens, William F., Watts, LaVaughn F.
• Primary Examiner(s): Ray, Gopal C.
• Application Number:
  US08/621,741
• Time in Patent Office: 1,034 Days
• Field of Search: 395/750, 395/750.07, 395/750.01, 364/707, 365/226, 323/271
• US Class Current: 713/330
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24

Abstract

This is a system and method of intelligently terminating power to a computing device. The system may comprise: a processing device; a power source connected to the processing device; a switch connected to the power source; and a control system run by the processing device and connected to the power source and the switch. In addition, the system may include a deadman timer which provides a fail-safe operation. Further, the system may include a method and apparatus for executing an orderly shut down procedure for software and hardware. Moreover, the system could be tied to a thermal and/or power management system. Additionally, the system could initiate an orderly shut down of peripheral devices connected to the system serially or by parallel connections. Other devices, systems and methods are also described.

Claims

1. An apparatus, comprising:

a means for user input;

a means for output;

a processor coupled to said means for user input and means for output;

a software controlled switch for coupling power to said processor, said switch having a first mode of operation wherein power to said processor is terminated substantially simultaneously with user actuation of said switch, and a second mode of operation wherein power to said processor is terminated upon completion of both said switch being user actuated and software releasing control of said switch at a time not substantially simultaneous with user actuation of said switch; and

a timer circuit coupled to said switch, said timer circuit including a power off timer with a set value that initiates a shut down procedure when said power off timer times out.

2. The apparatus of claim 1, wherein said software controlled switch further includes a third mode of operation wherein power to said processor is terminated upon completion of said switch being user actuated and one of said software releasing control of said switch within a time period less than said set value and said power off timer completing said shut down procedure in the event said software does not release control of said switch within a time period less than said set value.

3. The apparatus of claim 2, wherein said software sets said power off timer to time out instantly upon completion of both said switch being user actuated and said software releasing control of said switch prior to said time period reaching said set value.

4. The apparatus of claim 1, wherein said software controlling said switch in said second mode of operation initiates a software shutdown process.

5. The apparatus of claim 1, wherein said software controlling said switch in said second mode of operation initiates a hardware shutdown process.

6. The apparatus of claim 1, wherein said software controlling said switch in said second mode of operation initiates a software and hardware shutdown process.

7. The apparatus of claim 1, wherein said set value is a default value.

8. The apparatus of claim 1, wherein said software sets said default value.

9. The apparatus of claim 1, wherein a user of said apparatus sets said default value.

10. The apparatus of claim 1, wherein said set value is resetable by said processor.

11. The apparatus of claim 1, wherein said processor is a central processing unit (CPU).

12. The apparatus of claim 1, wherein said processor is an application processor.

13. The apparatus of claim 1, wherein said apparatus is a computer.

14. The computer of claim 13, wherein said software is implemented in the bootup process of said computer.

15. The computer of claim 13, wherein said software is implemented when a user of said computer actuates said switch.

16. The computer of claim 13, wherein said software controlled switch further includes a power failure mode wherein a power shut down procedure is initiated in the event that battery power level drops below a predetermined value.

17. The computer of claim 13, wherein when said power switch is actuated to be on, the system boots, the software boots, the Basic Input/Output System (BIOS) initializes and then the timer is set to zero and the power switch is activated in said first mode of operation.

18. The computer of claim 17, wherein subsequent to said power switch being activated in said first mode of operation, and through the process of initializing the rest of the computer'"'"'s system, said software determines whether or not to change said switch from said first mode of operation to said second mode of operation.

19. The computer of claim 13, wherein said switch is programmed to watch for a System Management Interrupt (SMI).

20. The computer of claim 19, wherein said switch is set to act real time upon an SMI.

21. The computer of claim 20, wherein when the SMI interrupt is detected, the heads of a hard drive coupled to said processor are positioned and parked, the power to the hard drive and a display coupled to the processor is terminated, after which the CMOS parameters that need to be saved are saved.

22. The computer of claim 13, wherein said switch is set to act upon an SMI at a later time.

23. The computer of claim 22, wherein said software allows the computer'"'"'s operating system and other programs to prepare for shut down, including but not limited to, closing files, updating any pertinent parameters, after which the heads of a hard drive coupled to said processor are positioned and parked, the power to the hard drive and a display coupled to the processor is terminated, after which the CMOS parameters that need to be saved are saved.

24. A computer, comprising:

a display;

a keyboard;

a central processor unit (CPU) coupled to said display and said keyboard;

a software controlled switch for coupling power to said central processing unit (CPU), said switch having a first mode of operation wherein power to said processor is terminated substantially simultaneously with user actuation of said switch, and a second mode of operation wherein power to said central processing unit (CPU) is terminated upon completion of both said switch being user actuated and software releasing control of said switch at a time not substantially simultaneous with user actuation of said switch; and

a timer circuit coupled to said switch, said timer circuit including a power off timer with a set value that initiates a shut down procedure when said power off timer times out.

25. The computer of claim 24, wherein said software controlled switch further includes a third mode of operation wherein power to said central processing unit (CPU) is terminated upon completion of said switch being user actuated and one of said software releasing control of said switch within a time period less than said set value and said power off timer completing said shut down procedure in the event said software does not release control of said switch within a time period less than said set value.

26. The computer of claim 25, wherein said software sets said power off timer to time out instantly upon completion of both said switch being actuated and said software releasing control of said switch prior to said time period reaching said set value.

27. The computer of claim 24, wherein said software controlling said switch in said second mode of operation initiates a software shutdown process.

28. The computer of claim 24, wherein said software controlling said switch in said second mode of operation initiates a hardware shutdown process.

29. The computer of claim 24, wherein said software controlling said switch in said second mode of operation initiates a software and hardware shutdown process.

30. The computer of claim 24, wherein said set value is a default value.

31. The computer of claim 24, wherein said software sets said default value.

32. The computer of claim 24, wherein a user of said apparatus sets said default value.

33. The computer of claim 24, wherein said set value is resetable by said central processing unit (CPU).

34. A method of controlling power to an apparatus, comprising the step of:

providing a user input;

providing an output;

providing a processor coupled to said user input and output;

providing a software controlled switch for coupling power to said processor, said switch having a first mode of operation wherein power to said processor is terminated substantially simultaneously with user actuation of said switch, and a second mode of operation wherein power to said processor is terminated upon completion of both said switch being user actuated and software releasing control of said switch at a time not substantially simultaneous with user actuation of said switch; and

providing a timer circuit for coupling to said switch, said timer circuit including a power off timer with a set value that initiates a shut down procedure when said power off timer times out.

35. The method of claim 34, wherein said software controlled switch further includes a third mode of operation wherein power to said processor is terminated upon completion of said switch being user actuated and one of said software releasing control of said switch within a time period less than said set value and said power off timer completing said shut down procedure in the event said software does not release control of said switch within a time period less than said set value.

36. The method of claim 35, wherein said software sets said power off timer to time out instantly upon completion of both said switch being user actuated and said software releasing control of said switch prior to said time period reaching said set value.

37. The method of claim 34, wherein said software controlling said switch in said second mode of operation initiates a software shutdown process.

38. The method of claim 34, wherein said software controlling said switch in said second mode of operation initiates a hardware shutdown process.

39. The method of claim 34, wherein said software controlling said switch in said second mode of operation initiates a software and hardware shutdown process.

40. The method of claim 34, wherein said set value is a default value.

41. The method of claim 34, wherein said software sets said default value.

42. The method of claim 34, wherein a user of said apparatus sets said default value.

43. The method of claim 34, wherein said set value is resetable by said processor.

44. The method of claim 34, wherein said processor is a central processing unit (CPU).

45. The method of claim 34, wherein said processor is an application processor.

46. The method of claim 34, wherein said apparatus is a computer.

47. The method of claim 46, wherein said software is implemented in the bootup process of said computer.

48. The method of claim 46, wherein said software is implemented when a user of said computer actuates said switch.

49. The method of claim 46, wherein said software controlled switch further includes a power failure mode wherein a power shut down procedure is initiated in the event that battery power level drops below a predetermined value.

50. The method of claim 46, wherein when said power switch is actuated to be on, the system boots, the software boots, the Basic Input/Output System (BIOS) initializes and then the timer is set to zero and the power switch is activated in said first mode of operation.

51. The method of claim 50, wherein subsequent to said power switch being activated in said first mode of operation, and through the process of initializing the rest of the computer'"'"'s system, said software determines whether or not to change said switch from said first mode of operation to said second mode of operation.

52. The method of claim 51, wherein said software allows the computer'"'"'s operating system and other programs to prepare for shut down, including but not limited to, closing files, updating any pertinent parameters, after which the heads of a hard drive coupled to said processor are positioned and parked, the power to the hard drive and a display coupled to the processor is terminated, after which the CMOS parameters that need to be saved are saved.

53. The method of claim 46, wherein said switch is programmed to watch for a System Management Interrupt (SMI).

54. The method of claim 53, wherein said switch is set to act real time upon an SMI.

55. The method of claim 54, wherein when the SMI interrupt is detected, the heads of a hard drive coupled to said processor are positioned and parked, the power to the hard drive and a display coupled to the processor is terminated, after which the CMOS parameters that need to be saved are saved.

56. The method of claim 46, wherein said switch is set to act upon an SMI at a later time.

57. An apparatus, comprising:

a means for user input;

a means for output;

a processor coupled to said means for user input and means for output;

circuitry for coupling power to said processor, said circuitry having a first mode of operation wherein power to said processor is terminated substantially simultaneously with user actuation of a switch, and a second mode of operation wherein power to said processor is terminated upon completion of both said switch being user actuated and software releasing control of said circuitry at a time not substantially simultaneous with user actuation of said switch; and

a timer circuit coupled to said circuitry, said timer circuit including a power off timer with a set value that initiates a shut down procedure when said power off timer times out.

58. An apparatus, comprising:

a means for user input;

a means for output;

a processor coupled to said means for user input and means for output;

a software program executed on said processor, said software program facilitating a first mode of operation wherein power to said processor is terminated substantially simultaneously with user actuation of a switch, and a second mode of operation wherein power to said processor is terminated upon completion of both said switch being user actuated and said software program triggering said termination of power at a time not substantially simultaneous with user actuation of said switch; and

a timer function for initiating a termination of power to said processor when said timer times out.

59. The apparatus of claim 58, wherein said timer function is performed by hardware.