Memory LSI with arithmetic logic processing capability, main memory system using the same, and method of controlling main memory system
First Claim
1. A main memory with arithmetic logic processing capability, comprising:
- a memory bus;
k first memories (k is an integer equal to or more than
0) connected to said memory bus, for storing data; and
m second memories with arithmetic logic processing capability (m is an integer equal to or more than
1) connected to said memory bus, wherein each of said m second memories comprises;
a memory section for storing data, andan arithmetic logic processing section for performing a first processing to at least a part of said data stored in said memory section in response to a first instruction inputted via said memory bus, and for allowing a result of said first processing to be outputted onto said memory bus in response to a second instruction inputted via said memory bus.
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Accused Products
Abstract
In a main memory with arithmetic logic processing capability, k first memories (k is an integer equal to or more than 0) are connected to a memory bus, for storing data. M second memories with arithmetic logic processing capability (m is an integer equal to or more than 1) are also connected to the memory bus. Each of the m second memories includes a memory section for storing data, and an arithmetic logic processing section. The arithmetic logic processing section performs a first processing to at least a part of the data stored in the memory section in response to a first instruction inputted via the memory bus, and allows a result of the first processing to be outputted onto the memory bus in response to a second instruction inputted via the memory bus. The arithmetic logic processing section may further includes a macro code RAM for storing macro codes. The main memory with arithmetic logic processing capability and a memory device with arithmetic logic processing capability used in the same have compatibility with a corresponding main memory and a corresponding memory device.
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Citations
33 Claims
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1. A main memory with arithmetic logic processing capability, comprising:
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a memory bus; k first memories (k is an integer equal to or more than
0) connected to said memory bus, for storing data; andm second memories with arithmetic logic processing capability (m is an integer equal to or more than
1) connected to said memory bus, wherein each of said m second memories comprises;a memory section for storing data, and an arithmetic logic processing section for performing a first processing to at least a part of said data stored in said memory section in response to a first instruction inputted via said memory bus, and for allowing a result of said first processing to be outputted onto said memory bus in response to a second instruction inputted via said memory bus. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A main memory with arithmetic logic processing capability, comprising:
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a memory bus; k first memories (k is an integer equal to or more than
0) connected to said memory bus, for storing data; andm second memories with arithmetic logic processing capability (m is an integer equal to or more than
1) connected to said memory bus, wherein each of said m second memories comprises;a memory section for storing data, a storing section for storing at least a macro code, and an arithmetic logic processing section for executing said at least a macro code in response to a first instruction inputted via said memory bus to perform a first processing to at least a part of said data stored in said memory section, and for allowing a result of said first processing to be outputted onto said memory bus in response to a second instruction inputted via said memory bus. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A memory device with arithmetic logic processing capability, comprising:
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a memory bus connected to external terminals; an internal bus; a dynamic random access memory (DRAM) section connected between said memory bus and said internal bus; and an arithmetic logic processing section connected between said memory bus and said internal bus, for performing a first processing to at least a part of data stored in said DRAM section in response to a first instruction inputted via said memory bus, and for allowing a result of said first processing to be outputted onto said memory bus in response to a second instruction inputted via said memory bus. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30)
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31. A method of controlling a main memory with arithmetic logic processing capability in a processor system including a processor, said main memory comprising at least one memory device with arithmetic logic processing capability, comprising the steps of:
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issuing a first instruction from said processor to said memory device via a memory bus; performing a processing to at least a part of data stored in said memory section in said memory device in response to said first instruction; storing a processing result in said memory device; issuing a second instruction from said processor to said memory device via said memory bus; and outputting a data designating the processing result to said processor in response to said second instruction inputted via said memory bus. - View Dependent Claims (32, 33)
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Specification