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Memory LSI with arithmetic logic processing capability, main memory system using the same, and method of controlling main memory system

  • US 5,862,396 A
  • Filed: 07/21/1997
  • Issued: 01/19/1999
  • Est. Priority Date: 08/02/1996
  • Status: Expired due to Term
First Claim
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1. A main memory with arithmetic logic processing capability, comprising:

  • a memory bus;

    k first memories (k is an integer equal to or more than

         0) connected to said memory bus, for storing data; and

    m second memories with arithmetic logic processing capability (m is an integer equal to or more than

         1) connected to said memory bus, wherein each of said m second memories comprises;

    a memory section for storing data, andan arithmetic logic processing section for performing a first processing to at least a part of said data stored in said memory section in response to a first instruction inputted via said memory bus, and for allowing a result of said first processing to be outputted onto said memory bus in response to a second instruction inputted via said memory bus.

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