Self-aligned edge control in silicon on insulator

• US 5,863,823 A
• Filed: 03/21/1995
• Issued: 01/26/1999
• Est. Priority Date: 07/12/1993
• Status: Expired due to Term

• Current Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Burgener, Mark L.
• Primary Examiner(s): DANG, TRUNG Q
• Application Number:
  US08/408,750
• Time in Patent Office: 1,407 Days
• Field of Search: 437/63, 437/61, 437/62, 437/69, 437/28, 438/295, 438/297, 438/298, 438/299, 438/410, 438/517
• US Class Current: 438/295
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02694 Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76281 Lateral isolation by selective oxidation of silicon
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78657 SOS transistors
• CPC Class Codes: H10B 10/15 comprising a resistor load element

Abstract

An improved process and structure for channel stop in silicon on insulator using LOCOS isolation are disclosed. Advantages include decreased ion dose requirements; reduced processing time; smaller ΔW characteristics, thus, small transistor size and more precise process control over the edge of a MOSFET. The process also makes possible a wide range of transistor design capabilities and improved transistor operating parameters.

Claims

1. A method for isolating an active region of a semiconductor layer from another region of the semiconductor layer comprising the steps of:

providing a layer of silicon on an insulating substrate;

forming a pad oxide layer on the layer of silicon;

providing a layer of silicon nitride on the pad oxide layer;

providing a photoresist layer over a portion of the layer of silicon nitride such that the photoresist layer is adapted to define the active region in the silicon layer wherein the active region is adapted for forming a transistor;

removing selected portions of the silicon nitride layer as defined by the photoresist layer;

removing the photoresist layer to expose a silicon nitride mask that covers portions of the active region;

oxidizing portions of the silicon layer as allowed by the silicon nitride mask to form a field oxide such that the silicon layer is oxidized at least in part through to the insulating substrate and such that an edge of the active region extends between the field oxide and the insulating substrate; and

implanting ions of a conductivity determining material in the edge of the active region after the portions of the silicon layer have been oxidized such that the ions are blocked by the silicon nitride mask from the portions of the active region that are covered by the silicon nitride mask and such that the ions are self-aligned in the edge of the active region by the silicon nitride mask.

2. The method of claim 1 wherein the step of providing the layer of silicon on the insulating substrate comprises the step of limiting the layer of silicon to a thickness of about 1,500 Å

or less.

3. The method of claim 1 wherein the step of forming the pad oxide layer comprises the step of limiting the thickness of the pad oxide layer to a range of about 100-150 Å

.

4. The method of claim 1 wherein the step of oxidizing the portions of the silicon layer comprises the step of thermally oxidizing the silicon layer at a temperature in a range of about 900°

C.-1000°

C.

5. The method of claim 1 wherein the step of providing a layer of silicon nitride further comprises the step of limiting the thickness of said silicon nitride layer to a range of about 750-2,000 Å

.

6. The method of claim 1 wherein the step of implanting ions of a conductivity determining material further comprises the steps of:

providing a second layer of photoresist after the step of oxidizing portions of the silicon but before the step of implanting ions to block the ions of the conductivity determining material from selected regions in the layer of silicon;

implanting boron ions into unblocked regions of the field oxide and into the edge of the active region.

7. The method of claim 6 wherein the step of implanting boron ions further comprises implanting the boron ions having a dosage in a range of about 1×

10¹⁴ /cm² to 10×

10¹⁴ /cm² at an implantation energy having a range of about 35-65 keV.

14. The method claim 1 wherein the insulating substrate comprises sapphire.

8. A method for making a MOSFET characterized by a small Δ

W characteristic comprising the steps of;

providing a substrate;

providing a semiconductor layer having a thickness of about 1,500 Å

or less on the substrate,

providing an oxidized layer having a thickness of at least about 100 Å

on a portion of the semiconductor layer;

providing a silicon nitride layer having a thickness of at least about 750 Å

on the oxidized layer;

defining an active region for the MOSFET transistor in the semiconductor layer by oxidizing portions of the semiconductor layer where the active region is not desired;

oxidizing the semiconductor layer to grow a field oxide through to the substrate at locations not covered by the silicon nitride layer wherein the field oxide is grown such that an edge of the active region extends between the field oxide and the insulating substrate; and

implanting ions of a conductivity determining material through the field oxide into the edge of the active region such that the ions are self-aligned by the silicon nitride layer.

9. The method of claim 8 further comprising the step of thinning the field oxide after the step of oxidizing the semiconductor layer.

10. The method of claim 9 wherein the step of implanting ions of a conductivity determining material includes the step of implanting ions selected from the group consisting of boron, arsenic and phosphorus.

11. The method of claim 10 wherein the step of implanting ions of a conductivity determining material further comprises the step of implanting boron ions having a dosage in a range of about 1×

10¹⁴ cm² to 10×

10 ¹⁴ cm² at an implant energy of a 35-65 keV.

15. The method of claim 8, wherein the substrate comprises sapphire.

12. A method for isolating an active region in a semiconductor layer on an insulating substrate wherein the active region is adapted for use in a MOSFET, the method comprising:

providing the insulating substrate wherein the substrate has a major surface;

providing the semiconductor layer on the major surface of the insulating substrate;

providing the active region in the semiconductor layer;

providing a nitride mask that covers a portion of the active region and that defines an area of the active region for receiving ions of a conductivity determining material;

providing a field oxide adjacent to the defined area of the active region;

removing a portion of the field oxide layer;

after the step of removing the portion of the field oxide layer, implanting ions from the group consisting of boron, arsenic and phosphorus through the field oxide and into the defined area of the active region such that the implanted ions are self-aligned by the nitride mask.

13. The method of claim 12 wherein the step of implanting ions further comprises the step of implanting boron ions having a dosage in a range of about 1×

10¹⁴ cm² to 10×

10¹⁴ cm² at an implant energy of a 35-65 keV.

16. The method of claim 12 wherein the insulating substrate comprises sapphire.