Hybrid polysilicon/amorphous silicon TFT and method of fabrication

• US 5,864,150 A
• Filed: 05/21/1998
• Issued: 01/26/1999
• Est. Priority Date: 06/27/1997
• Status: Expired due to Term

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Lin, Kang-Cheng
• Primary Examiner(s): Ngo , Ngan V.
• Application Number:
  US09/082,778
• Time in Patent Office: 250 Days
• Field of Search: 257/59, 257/61, 257/66, 257/72, 257/75
• US Class Current: 257/61
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/78678 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

The present invention discloses a hybrid polysilicon/amorphous silicon TFT device for switching a LCD and a method for fabrication wherein a n⁺ doped amorphous silicon layer is advantageously used as a mask during a laser annealing process such that only a selected portion of a hydrogenated amorphous silicon layer is converted to a crystalline structure while other portions retain their amorphous structure. As a result, a polysilicon TFT and at least one amorphous silicon TFT are formed in the same structure and the benefits of both a polysilicon TFT and amorphous silicon TFT such as a high charge current and a low leakage current are retained in the hybrid structure.

Claims

1. A hybrid polysilicon/amorphous silicon thin film transistor (TFT) device comprising:

a substrate having a gate and a first insulating layer formed thereon,

a layer of hydrogenated amorphous silicon on said first insulating layer, said hydrogenated amorphous silicon layer having a center portion converted to a crystalline state forming a polysilicon TFT, and at least one hydrogenated amorphous silicon TFT formed by the hydrogenated amorphous silicon layer surrounding said center portion,

an insulator formed of a second insulating material on said hydrogenated amorphous silicon layer,

a n⁺ doped hydrogenated amorphous silicon layer on top of said hydrogenated amorphous silicon layer and partially said insulator except a window portion exposing a center portion of said insulator having substantially the same area as the center crystalline portion of said hydrogenated amorphous silicon layer, and

electrodes for drain, source and gate for providing electrical communication to said hybrid TFT formed by said polysilicon TFT and said at least one hydrogenated amorphous silicon TFT.

2. A device according to claim 1, wherein said first insulation layer and said second insulating layers are formed of silicon oxide or silicon nitride.

3. A device according to claim 1, wherein said n⁺ doped amorphous silicon layer comprises boron dopant.

4. A device according to claim 1, wherein said hydrogenated amorphous silicon layer having a thickness between about 20 nm and about 200 nm, preferably between about 20 nm and about 100 nm.

5. A device according to claim 1, wherein said n⁺ doped amorphous silicon layer having a thickness between about 10 nm and about 500 nm, preferably between about 10 nm and about 100 nm.

6. A device according to claim 1, wherein said substrate is formed of a ceramic substrate.

7. A device according to claim 1, wherein said gate is formed of a refractory metal.

8. A device according to claim 1, wherein said gate is formed of a material selected from the group consisting of Cr, Mo, Ta and Ti.