Insulated gate semiconductor device structure to prevent a reduction in breakdown voltage
First Claim
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1. An insulated gate semiconductor device, comprising:
- a semiconductor substrate of a first conductivity type, having a first major surface and a second major surface;
a first semiconductor layer of a second conductivity type disposed on said first major surface of said semiconductor substrate, having a first surface and at least one trench with an opening at said surface reaching said first major surface of said semiconductor substrate in a direction vertical to said surface of said first semiconductor layer;
an insulating film formed over an inside wall of said at least one trench;
a conductor disposed inside said at least one trench, being opposed to said first semiconductor layer with said insulating film therebetween;
a second semiconductor layer of the first conductivity type disposed in a portion of said surface of said first semiconductor layer, being opposed to said conductor with said insulating film therebetween;
an insulating layer so disposed as to cover a portion of a surface of said second semiconductor layer and a surface of said conductor;
a third semiconductor layer of the second conductivity type disposed between said first major surface of said semiconductor substrate and said first semiconductor layer and formed along a second surface of said first semiconductor layer, the impurity concentration of said third semiconductor layer being lower than that of said first semiconductor layer;
a first main electrode disposed on said surfaces of said first and second semiconductor layers; and
a second main electrode disposed on said second major surface of said semiconductor substrate;
wherein said at least one trench includes first and second trenches and said third semiconductor layer is located between said first and second trenches, and wherein said conductor is insulated from the first, second and third semiconductor layers.
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Abstract
A P- layer (51) is formed between a P base layer (43) and an N- layer (42) so as to be in contact with the P base layer (43), facing an insulating film (46) of a trench (45) with the N- layer (42) between. In the configuration, a depletion layer extends to the P- layer (51) to relieve an electric field at a tip end portion of the trench (45) and a channel length can be lessened. Therefore, it is possible to provide an insulated gate semiconductor device of high breakdown voltage and low On-resistance.
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Citations
16 Claims
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1. An insulated gate semiconductor device, comprising:
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a semiconductor substrate of a first conductivity type, having a first major surface and a second major surface; a first semiconductor layer of a second conductivity type disposed on said first major surface of said semiconductor substrate, having a first surface and at least one trench with an opening at said surface reaching said first major surface of said semiconductor substrate in a direction vertical to said surface of said first semiconductor layer; an insulating film formed over an inside wall of said at least one trench; a conductor disposed inside said at least one trench, being opposed to said first semiconductor layer with said insulating film therebetween; a second semiconductor layer of the first conductivity type disposed in a portion of said surface of said first semiconductor layer, being opposed to said conductor with said insulating film therebetween; an insulating layer so disposed as to cover a portion of a surface of said second semiconductor layer and a surface of said conductor; a third semiconductor layer of the second conductivity type disposed between said first major surface of said semiconductor substrate and said first semiconductor layer and formed along a second surface of said first semiconductor layer, the impurity concentration of said third semiconductor layer being lower than that of said first semiconductor layer; a first main electrode disposed on said surfaces of said first and second semiconductor layers; and a second main electrode disposed on said second major surface of said semiconductor substrate;
wherein said at least one trench includes first and second trenches and said third semiconductor layer is located between said first and second trenches, and wherein said conductor is insulated from the first, second and third semiconductor layers. - View Dependent Claims (2, 3, 16)
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4. An insulated gate semiconductor, comprising:
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a semiconductor substrate of a first conductivity type, having a first major surface and a second major surface; a first semiconductor layer of a second conductivity type disposed on said first major surface of said semiconductor substrate, having a surface and at least one trench with an opening at said surface reaching said first major surface of said semiconductor substrate in a direction vertical to said surface of said first semiconductor layer; an insulating film formed over an inside wall of said at least one trench; a conductor disposed inside said at least one trench, being opposed to said first semiconductor layer with said insulating film therebetween; a second semiconductor layer of the first conductivity type disposed in a portion of said surface of said first semiconductor layer, being opposed to said conductor with said insulating film therebetween; an insulating layer so disposed as to cover a portion of a surface of said second semiconductor layer and a surface of said conductor; a third semiconductor layer of the second conductivity type disposed between said first major surface of said semiconductor substrate and said first semiconductor layer, the impurity concentration of which is lower than that of said first semiconductor layer; a first main electrode disposed on said surfaces of said first and second semiconductor layers; and a second main electrode disposed on said second major surface of said semiconductor substrate; wherein said third semiconductor layer is opposed to said at least one trench with a portion of said semiconductor substrate therebetween. - View Dependent Claims (5, 6)
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7. An insulated gate semiconductor device, comprising:
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a semiconductor substrate of a first conductivity type, having a first major surface and a second major surface; a first semiconductor layer of a second conductivity type disposed on said first major surface of said semiconductor substrate, having a surface, at least one first trench and at least one second trench, said at least one first trench and said at least one second trench each having an opening at said surface, being parallel and reaching said first major surface of said semiconductor substrate; a first insulating film formed over an inside wall of said at least one first trench; a second insulating film formed over an inside wall of said at least one second trench; a first conductor disposed inside said at least one first trench, being opposed to said first semiconductor layer with said first insulating film therebetween; a second conductor disposed inside said at least one second trench, being opposed to said first semiconductor layer with said second insulating film therebetween; a second semiconductor layer of the first conductivity type disposed in a portion of said surface of said first semiconductor layer, being opposed to said first conductor with said first insulating film therebetween; an insulating layer so disposed as to cover a surface of said first conductor and a portion of a surface of said second semiconductor layer; a first main electrode short circuited to said second conductor and disposed on said surfaces of said first and second semiconductor layers; a second main electrode disposed on said second major surface of said semiconductor substrate. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15)
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Specification