Insulated gate semiconductor device structure to prevent a reduction in breakdown voltage

• US 5,864,159 A
• Filed: 07/25/1997
• Issued: 01/26/1999
• Est. Priority Date: 12/13/1994
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Takahashi, Hideki
• Primary Examiner(s): Wallace, Valencia Martin
• Application Number:
  US08/900,825
• Time in Patent Office: 550 Days
• Field of Search: 257/327, 257/329, 257/330, 257/331, 257/333, 257/334, 257/267, 257/328, 257/339, 438/267, 438/270
• US Class Current: 257/330
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A P^- layer (51) is formed between a P base layer (43) and an N^- layer (42) so as to be in contact with the P base layer (43), facing an insulating film (46) of a trench (45) with the N^- layer (42) between. In the configuration, a depletion layer extends to the P^- layer (51) to relieve an electric field at a tip end portion of the trench (45) and a channel length can be lessened. Therefore, it is possible to provide an insulated gate semiconductor device of high breakdown voltage and low On-resistance.

Claims

1. An insulated gate semiconductor device, comprising:

a semiconductor substrate of a first conductivity type, having a first major surface and a second major surface;

a first semiconductor layer of a second conductivity type disposed on said first major surface of said semiconductor substrate, having a first surface and at least one trench with an opening at said surface reaching said first major surface of said semiconductor substrate in a direction vertical to said surface of said first semiconductor layer;

an insulating film formed over an inside wall of said at least one trench;

a conductor disposed inside said at least one trench, being opposed to said first semiconductor layer with said insulating film therebetween;

a second semiconductor layer of the first conductivity type disposed in a portion of said surface of said first semiconductor layer, being opposed to said conductor with said insulating film therebetween;

an insulating layer so disposed as to cover a portion of a surface of said second semiconductor layer and a surface of said conductor;

a third semiconductor layer of the second conductivity type disposed between said first major surface of said semiconductor substrate and said first semiconductor layer and formed along a second surface of said first semiconductor layer, the impurity concentration of said third semiconductor layer being lower than that of said first semiconductor layer;

a first main electrode disposed on said surfaces of said first and second semiconductor layers; and

a second main electrode disposed on said second major surface of said semiconductor substrate;

wherein said at least one trench includes first and second trenches and said third semiconductor layer is located between said first and second trenches, and wherein said conductor is insulated from the first, second and third semiconductor layers.

2. The insulated gate semiconductor device of claim 1, wherein said at least one trench includes at least said first and second trenches as a plurality of trenches,

said second semiconductor layer includes a plurality of fourth semiconductor layers adjoining said plurality of trenches along said both sides of said opening, and

two of said fourth semiconductor layers existing between adjacent ones of said plurality of trenches are arranged so that said first semiconductor layer may be laid between said two fourth semiconductor layers.

3. The insulated gate semiconductor device of claim 1, wherein said at least one trench includes at least said first and second trenches as a plurality of trenches, and

said second semiconductor layers include a plurality of fourth semiconductor layers which extend in parallel with each other, intersecting openings of said plurality of trenches.

16. The insulated gate semiconductor device of claim 1, wherein said third semiconductor layer contacts said first semiconductor layer.

4. An insulated gate semiconductor, comprising:

a semiconductor substrate of a first conductivity type, having a first major surface and a second major surface;

a first semiconductor layer of a second conductivity type disposed on said first major surface of said semiconductor substrate, having a surface and at least one trench with an opening at said surface reaching said first major surface of said semiconductor substrate in a direction vertical to said surface of said first semiconductor layer;

an insulating film formed over an inside wall of said at least one trench;

a conductor disposed inside said at least one trench, being opposed to said first semiconductor layer with said insulating film therebetween;

a second semiconductor layer of the first conductivity type disposed in a portion of said surface of said first semiconductor layer, being opposed to said conductor with said insulating film therebetween;

an insulating layer so disposed as to cover a portion of a surface of said second semiconductor layer and a surface of said conductor;

a third semiconductor layer of the second conductivity type disposed between said first major surface of said semiconductor substrate and said first semiconductor layer, the impurity concentration of which is lower than that of said first semiconductor layer;

a first main electrode disposed on said surfaces of said first and second semiconductor layers; and

a second main electrode disposed on said second major surface of said semiconductor substrate;

wherein said third semiconductor layer is opposed to said at least one trench with a portion of said semiconductor substrate therebetween.

5. The insulated gate semiconductor device of claim 4, wherein

said at least one trench includes a plurality of trenches,

said second semiconductor layer includes a plurality of fourth semiconductor layers adjoining said plurality of trenches, and

two of said fourth semiconductor layers existing between adjacent ones of said plurality of trenches are arranged so that said first semiconductor layer may be laid between said two fourth semiconductor layers.

6. The insulated gate semiconductor device of claim 4, wherein

said at least one trench includes a plurality of trenches, and

said second semiconductor layers include a plurality of fourth semiconductor layers which extend in parallel with each other, intersecting openings of said plurality of trenches.

7. An insulated gate semiconductor device, comprising:

a semiconductor substrate of a first conductivity type, having a first major surface and a second major surface;

a first semiconductor layer of a second conductivity type disposed on said first major surface of said semiconductor substrate, having a surface, at least one first trench and at least one second trench, said at least one first trench and said at least one second trench each having an opening at said surface, being parallel and reaching said first major surface of said semiconductor substrate;

a first insulating film formed over an inside wall of said at least one first trench;

a second insulating film formed over an inside wall of said at least one second trench;

a first conductor disposed inside said at least one first trench, being opposed to said first semiconductor layer with said first insulating film therebetween;

a second conductor disposed inside said at least one second trench, being opposed to said first semiconductor layer with said second insulating film therebetween;

a second semiconductor layer of the first conductivity type disposed in a portion of said surface of said first semiconductor layer, being opposed to said first conductor with said first insulating film therebetween;

an insulating layer so disposed as to cover a surface of said first conductor and a portion of a surface of said second semiconductor layer;

a first main electrode short circuited to said second conductor and disposed on said surfaces of said first and second semiconductor layers;

a second main electrode disposed on said second major surface of said semiconductor substrate.

8. The insulated gate semiconductor device of claim 7, wherein

said at least one first trench includes a plurality of third trenches,

said at least one second trench includes a plurality of fourth trenches,

said second semiconductor layer includes a plurality of third semiconductor layers,

said third trenches and said fourth trenches are arranged to alternate with respect to each other, and

said third semiconductor layers adjoin said third trenches.

9. The insulated gate semiconductor device of claim 7, wherein

said at least one first trench includes a plurality of third trenches,

said at least one second trench includes a plurality of fourth trenches, said second semiconductor layer includes a plurality of third semiconductor layers,

said third trenches and said fourth trenches are arranged to alternate with respect to each other, and

said third semiconductor layers are disposed in such stripe shapes as to intersect said third trenches and said fourth trenches.

10. The insulated gate semiconductor device of claim 7, wherein

a plurality of third semiconductor layers of the second conductivity type, the impurity concentration of which is lower than that of said first semiconductor layer, are disposed in portions of said semiconductor substrate which are opposed to said first conductor at a bottom portion of said at least one first trench with said first insulating film therebetween and/or opposed to said second conductor at a bottom portion of said at least one second trench with said second insulating film therebetween.

11. The insulated gate semiconductor device claim 7, wherein

said at least one first trench includes a plurality of third trenches,

said at least one second trench includes a plurality of fourth trenches,

said second semiconductor layer includes a plurality of fourth semiconductor layers,

said third trenches and said fourth trenches are arranged to alternate with respect to each other, and

said fourth semiconductor layers adjoin said third trenches.

12. The insulated gate semiconductor device of claim 7, wherein

said at least one first trench includes a plurality of third trenches,

said at least one second trench includes a plurality of fourth trenches,

said second semiconductor layer includes a plurality of fourth semiconductor layers,

said third trenches and said fourth trenches are alternately arranged, and

said fourth semiconductor layers are disposed in such stripe shapes as to intersect said third trenches and said fourth trenches.

13. The insulated gate semiconductor device of claim 10, wherein said plurality of third semiconductor layers are disposed being opposed only to said second conductor in said at least one second trench with said second insulating film therebetween.

14. The insulated gate semiconductor device of claim 13, wherein

said at least one first trench includes a plurality of third trenches,

said at least one second trench includes a plurality of fourth trenches,

said second semiconductor layer includes a plurality of fourth semiconductor layers,

said third trenches and said fourth trenches are arranged to alternate with respect to each other, and

said fourth semiconductor layers adjoin said third trenches.

15. The insulated gate semiconductor device of claim 13, wherein

said at least one first trench includes a plurality of third trenches,

said at least one second trench includes a plurality of fourth trenches,

said second semiconductor layer includes a plurality of fourth semiconductor layers,

said third trenches and said fourth trenches are arranged to alternate with respect to each other, and

said fourth semiconductor layers are disposed in such stripe shapes as to intersect said third trenches and said fourth trenches.