Wrap-resistant ultra-thin integrated circuit package fabrication method

• US 5,864,175 A
• Filed: 05/10/1996
• Issued: 01/26/1999
• Est. Priority Date: 03/29/1993
• Status: Expired due to Term

• Current Assignee: OVID Data Company LLC (Intellectual Ventures LLC)
• Original Assignee: Staktek Corporation (Entorian Technologies)
• Inventors: Burns, Carmen D.
• Primary Examiner(s): Brown, Peter Toby
• Assistant Examiner(s): Oh, Edwin
• Application Number:
  US08/644,491
• Time in Patent Office: 991 Days
• Field of Search: 257/678, 257/683-686, 257/701-704, 257/706, 257/712, 257/713, 257/723, 257/724, 257/730, 257/787, 257/790, 257/796, 257/696
• US Class Current: 257/684
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2225/1029 the support being a lead frame
• CPC Class Codes: H01L 23/16 Fillings or auxiliary members in containers or encapsulations, e.g. centering rings H01L23/42, H01L23/552 take precedence
• CPC Class Codes: H01L 23/31 characterised by the arrangement or shape
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/4951 Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
• CPC Class Codes: H01L 23/49541 Geometry of the lead-frame
• CPC Class Codes: H01L 23/49555 the bent parts being the outer leads
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15747 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3511 : Warping
• CPC Class Codes: H05K 1/0201 : Thermal arrangements, e.g. for cooling, heating or preventing overheating
• CPC Class Codes: H05K 1/181 : associated with surface mounted components
• CPC Class Codes: H05K 3/3421 : Leaded components
• CPC Class Codes: H05K 7/023 : Stackable modules
• CPC Class Codes: Y10S 438/977 : Thinning or removal of substrate

Abstract

The present invention provides a method for fabricating modified integrated circuit packages that are ultra-thin and resist warping. The integrated circuit packages are made thinner by removing some of the casing material uniformly from the upper and lower major surfaces of the integrated circuit package. To prevent the resulting ultra-thin integrated circuit package from warping, a thin layer of material with a coefficient of thermal expansion less than that of silicon is mounted to the upper major surface of the package after some of the casing material has been removed uniformly from the upper major surface. Also, a thin layer of material with a coefficient of thermal expansion greater than that of silicon may be mounted to the lower major surface of the package after some of the casing material has been removed uniformly from the lower major surface. The result is an ultra-thin integrated circuit package that is thermally and mechanically balanced to prevent warping.

Claims

1. A warp-resistant integrated circuit package manufactured in accordance with a method comprising the steps of:

providing an integrated circuit package having planar upper and lower major surfaces, an integrated circuit die, and a neutral thermodynamic axis that coincides with a plane approximately through the center of said die;

reducing the overall thickness of said integrated circuit package by removing some casing material uniformly across said planar upper major surface;

mounting a thin layer of material, and having a coefficient of thermal expansion less than or equal to the coefficient of thermal expansion of silicon to said uniformly reduced planar upper major surface of said integrated circuit package, wherein said thin layer of material extends to the perimeter of said upper major surface; and

reducing the overall thickness of said integrated circuit package by removing some casing material uniformly across said planar lower major surface;

wherein said thin layer of material is mounted on said package exterior; and

wherein the thickness of said thin layer of material and its disposition relative to said selected axis are selected to minimize the vectorial summation of all moments acting on said package about said axis; and

wherein the moment associated with each layer of material forming said package is calculated using the equation;

space="preserve" listing-type="equation">m≈

(E)(h)(t)Δ

(a)Δ

(T)

where m is the moment of the layer;

E is the Young'"'"'s modulus of elasticity of the layer material;

h is the moment-arm distance of the center of the layer from said neutral thermodynamic axis;

t is the layer thickness;

Δ

(a) is the difference in CTE between the layer and the material containing the neutral thermodynamic axis; and

Δ

(T) is the temperature difference between assembly bonding temperature and operation temperature.

2. The package of claim 1, wherein all of said casing is removed from said lower major surface and some of said integrated circuit die is uniformly removed from said lower major surface.

3. The package of claim 1, further comprising a thin layer of material having a coefficient of thermal expansion greater than the coefficient of thermal expansion of silicon, said thin layer being mounted to said lower major surface of said integrated circuit package.

4. The package of claim 1, wherein a thin layer of material having a coefficient of thermal expansion approximately equal to that of said casing material is mounted to said lower major surface of said package.

5. The package of claim 3, wherein said material having a coefficient of thermal expansion greater than the coefficient of thermal expansion of silicon is aluminum.

6. The package of claim 3, wherein said material having a coefficient of thermal expansion greater than the coefficient of thermal expansion of silicon is copper.

7. A warp-resistant integrated circuit package of the type including an integrated circuit die, comprising:

(a) an integrated circuit package having a planar upper and lower major surface, an integrated circuit die, and a neutral thermodynamic axis that coincides with a plane approximately through the center of said die; and

(b) a thin layer of material and having a coefficient of thermal expansion less than or equal to the coefficient of thermal expansion of silicon mounted to said planar upper major surface of said integrated circuit package after said upper major surface has been uniformly reduced by removing some casing material uniformly across said upper major surface, wherein said thin layer of material extends to the perimeter of said upper major surface;

wherein the overall thickness of said integrated circuit package is again reduced by removing some casing material uniformly across said lower major surface; and

wherein said thin layer of material is mounted on said package exterior; and

wherein the thickness of said thin layer of material and its disposition relative to said selected axis is selected to minimize the vectorial summation of all moments acting on said package about said axis; and

wherein the moment associated with each layer of material forming said package is calculated using the equation;

space="preserve" listing-type="equation">m≈

(E)(h)(t)Δ

(a)Δ

(T)

where m is the moment of the layer;

E is the Young'"'"'s modulus of elasticity of the layer material;

h is the moment-arm distance of the center of the layer from said neutral thermodynamic axis;

t is the layer thickness;

Δ

(a) is the difference in CTE between the layer and the material containing the neutral thermodynamic axis; and

Δ

(T) is the temperature difference between assembly bonding temperature and operation temperature.

8. A warp-resistant integrated circuit package manufactured in accordance with a method comprising the steps of:

providing an integrated circuit package having planar upper and lower major surfaces;

reducing the overall thickness of said integrated circuit package by removing some casing material uniformly across said planar upper major surface;

mounting a thin layer of material having a coefficient of thermal expansion less than or equal to the coefficient of thermal expansion of silicon to said uniformly reduced planar upper major surface of said integrated circuit package; and

reducing the overall thickness of said integrated circuit package by removing some casing material uniformly across said planar lower major surface;

wherein said thin layer of material is mounted on said package exterior; and

wherein said thin layer of material is mounted to said upper major surface directly above said die and directly over extensions of each said surface that runs perpendicular to leads of said package.

9. A warp-resistant integrated circuit package of the type including an integrated circuit die, comprising:

(a) an integrated circuit package having an upper and a lower exterior major surface and a neutral thermodynamic axis that coincides with a plane approximately through the center of said die; and

(b) a thin layer of material with a coefficient of thermal expansion greater than the coefficient of thermal expansion of silicon mounted to said lower exterior major surface of said integrated circuit package.

wherein the thickness of said layer of material and its disposition relative to said selected axis is selected to minimize the vectorial summation of all moments acting on said package about said axis; and

wherein the moment associated with each layer of material forming said package is calculated using the equation;

space="preserve" listing-type="equation">m≈

(E)(h)(t)Δ

(a)Δ

(T)

where m is the moment of the layer;

E is the Young'"'"'s modulus of elasticity of the layer material;

h is the moment-arm distance of the center of the layer from said neutral thermodynamic axis;

t is the layer thickness;

Δ

(a) is the difference in CTE between the layer and the material containing the neutral thermodynamic axis; and

Δ

(T) is the temperature difference between assembly bonding temperature and operation temperature.

10. The package of claim 9, wherein prior to mounting said thin layer of material, the overall thickness of said integrated circuit package is reduced by removing some casing material uniformly across said lower major surface.

11. A warp-resistant integrated circuit package, of the type including a molded casing containing an integrated circuit die and having a neutral thermodynamic axis coinciding with a plane through the center of a lead frame, comprising:

(a) an integrated circuit package having an upper and a lower major surface;

(b) a thin layer of material with a coefficient of thermal expansion less than or equal to a coefficient of thermal expansion of silicon mounted to said upper major surface of said package;

wherein the thickness and orientation of a particular package layer, said package layers comprising said lead frame, and said casing above and below said axis, and said thin mounted layer of material, are selected in relation to each of the other package layers and to said neutral thermodynamic axis such that the vectorial summation of all moments of each of said package layers is as close to zero as possible; and

wherein the dimensions of each of said package layer is calculated using the equation;

space="preserve" listing-type="equation">m≈

(E)(h)(t)Δ

(a)Δ

(T)

where m is the moment of a particular package layer;

E is the Young'"'"'s modulus of elasticity of the material comprising each package layer;

h is the moment-arm distance of the center of the layer from the neutral thermodynamic axis;

t is the layer thickness;

Δ

(a) is the difference in CTE between the material comprising a particular package layer and the material comprising said lead frame which contains the neutral thermodynamic axis; and

Δ

(T) is the temperature difference between assembly bonding temperature and the operation or storage temperature of said package.

12. A warp-resistant integrated circuit package of the type including a molded casing containing an integrated circuit die and having a neutral thermodynamic axis coinciding with a plane through the center of a lead frame, comprising:

(a) an integrated circuit package having a first and a second major surface;

(b) a first thin layer of material, having a coefficient thermal expansion greater than the coefficient of thermal expansion of silicon, mounted to said first major surface of said package; and

(c) a second thin layer of material, having a coefficient thermal expansion less than the coefficient of thermal expansion of said first thin layer of material, mounted to said second major surface of said package;

wherein the thickness and orientation of said thin layers mounted to said package are selected in relation to each of said thin layers and to said neutral thermodynamic axis such that the vectorial summation of all moments of each of said thin layers is as close to zero as possible; and

wherein the dimensions of each of said thin layers of material are calculated using the equation;

space="preserve" listing-type="equation">m≈

(E)(h)(t)Δ

(a)Δ

(T)

where m is the moment of the thin layer;

E is the Young'"'"'s modulus of elasticity of the layer material;

h is the moment-arm distance of the center of the thin layer from the neutral thermodynamic axis;

t is the thin layer thickness;

Δ

(a) is the difference in CTE between the thin layer and the material containing the neutral thermodynamic axis; and

Δ

(T) is the temperature difference between assembly bonding temperature and the operation or storage temperature.