One-transistor adaptable analog storage element and array
First Claim
1. An analog storage element, said element disposed on an n-type semiconductor substrate and including:
- a p-type well disposed in the n-type substrate;
an N-channel MOS transistor disposed in said p-type well of the n-type semiconductor substrate, said N-channel MOS transistor including a source, a drain and a floating gate;
a tunneling electrode forming a tunneling junction with said floating gate;
a gate reference node capacitively coupled to said floating gates;
means for programming that simultaneously drives said gate reference node low while driving said tunnel electrode high, causing electron tunneling from said floating gate to said tunnel electrode;
means for reading the analog storage element by measuring an output current from said drain of said N-channel MOS transistor while driving said tunnel electrode low, said output current related to an amount of charge within said floating gate and a voltage potential placed at said source of said N-channel MOS transistor; and
means for erasing the analog storage element using means for forward biasing said p-type well with respect to said n-type substrate in order to inject minority electrons into said p-type well and using means for selectively raising said drain and source voltages of said N-channel floating gate transistor to accelerate said minority electrons enough to enable said minority electrons to migrate onto said floating gate of said N-channel MOS transistor.
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Accused Products
Abstract
An analog storage array according to the present invention is disposed on a semiconductor substrate. The array is arranged as a plurality of rows and a plurality of columns and includes a plurality of N-channel MOS transistors disposed in the rows and columns in a p-well in the semiconductor substrate. Each of the MOS transistors includes a source, a drain, and a floating gate forming a tunneling junction with a tunneling electrode. An input line is associated with each of the rows in the array. Each input line is connected to the source of each of the N-channel MOS transistors disposed in the row with which the input line is associated. A bias line is associated with each of the rows in the array. Each bias line is capacitively coupled to the floating gate of each of the N-channel MOS transistors disposed in the row with which the bias line is associated. A tunnel line is associated with each of the columns in the array. Each tunnel line connected to the tunneling electrode of each of the N-channel MOS transistors disposed in the column with which the bias line is associated. A current-sum line is associated with each of the columns in the array. Each current-sum line is connected to the drain of each of the N-channel MOS transistors disposed in the column with which the bias line is associated. Circuitry is provided for forward biasing said p-well with respect to the substrate. Circuitry is provided for simultaneously driving a selected one of the bias lines low while driving a selected one of the tunnel lines high, for raising the floating gate voltage of the one of the N-channel MOS transistors common to the selected one of the bias lines and the selected one of the tunnel lines.
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Citations
10 Claims
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1. An analog storage element, said element disposed on an n-type semiconductor substrate and including:
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a p-type well disposed in the n-type substrate; an N-channel MOS transistor disposed in said p-type well of the n-type semiconductor substrate, said N-channel MOS transistor including a source, a drain and a floating gate; a tunneling electrode forming a tunneling junction with said floating gate; a gate reference node capacitively coupled to said floating gates; means for programming that simultaneously drives said gate reference node low while driving said tunnel electrode high, causing electron tunneling from said floating gate to said tunnel electrode; means for reading the analog storage element by measuring an output current from said drain of said N-channel MOS transistor while driving said tunnel electrode low, said output current related to an amount of charge within said floating gate and a voltage potential placed at said source of said N-channel MOS transistor; and means for erasing the analog storage element using means for forward biasing said p-type well with respect to said n-type substrate in order to inject minority electrons into said p-type well and using means for selectively raising said drain and source voltages of said N-channel floating gate transistor to accelerate said minority electrons enough to enable said minority electrons to migrate onto said floating gate of said N-channel MOS transistor. - View Dependent Claims (2, 3, 4, 5)
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6. An analog storage array arranged as a plurality of rows and a plurality of columns, said array disposed on an n-type semiconductor substrate and including:
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a p-type well disposed in the n-type substrate; a plurality of N-channel MOS transistors disposed in the plurality of rows and columns in said p-type well of the n-type semiconductor substrate, said N-channel MOS transistor including a source, a drain and a floating gate; a tunneling electrode forming a tunneling junction with said floating gate; a gate reference node capacitively coupled to said floating gates a plurality of input line lines, each input line connected to the source of each of said plurality of N-channel MOS transistors disposed in the row with which said input line is associated; a plurality of bias lines, each bias line capacitively coupled to said floating gate of each of said plurality of N-channel MOS transistors disposed in the row with which said bias line is associated a plurality of tunnel lines, each tunnel line connected to said tunneling electrodes of said plurality of N-channel MOS transistors disposed in the column with which said bias line is associated; a plurality of current-sum lines, each current-sum line connected to said drain of each of said plurality of N-channel MOS transistors disposed in the column with which said bias line is associated; means for programming that simultaneously drives a selected one of said bias lines low while driving a selected one of said tunnel lines high, causing electron tunneling from the floating gate of one of said plurality of N-channel MOS transistors common to said selected one of said bias lines and said selected one of said tunnel lines; and means for reading a selected one of said plurality of N-channel MOS transistors by measuring an output current from a drain of a selected one of said plurality of N-channel MOS transistors while a selected one of said plurality of tunnel lines is driven low, said output current related to an amount of charge within said floating gate and a voltage potential placed at said source of said selected one of said plurality of N-channel MOS transistors; and means for erasing, said means for erasing having means for forward biasing said p-well with respect to the n-type substrate in order to inject minority electrons into said p-well and means for selectively raising the drain and source voltages of at least one of said N-channel floating gate transistors to accelerate said injected minority electrons enough to enable them to migrate onto the floating gate of said at least one of said N-channel floating gate transistors. - View Dependent Claims (7, 8, 9, 10)
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Specification