Apparatus for manipulation of display data
First Claim
1. A display circuit for manipulating an image to be viewed on a display device, said display circuit comprising:
- a display memory containing pixel data defining a first image;
an address counter for generating first addresses related to the order for reading the pixel data from the display memory for viewing the first image on the display device;
parameter memory for storing rotation and scaling parameters for manipulating the first image; and
a display operations controller for transforming the first addresses from the address counter into second addresses in accordance with the parameters from the parameter memory and for reading the pixel data in sequence from the display memory in accordance with the second addresses in synchronization with synchronization signals for the display device, the pixel data read from the display memory being outputted to the display device.
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Abstract
A display control circuit that enables efficient image rotation, and scaling of bit-mapped image data stored in image memory, in synchronization with dot clock, line, or frame timing of a target display device without requiring re-writing of the display memory contents. Addresses output from a memory address counter are modified by multiplication and summation with desired image display parameters to generate new addresses for retrieving desired image data from memory locations that are physically mapped to the modifications desired for a new output image. The basic image data is not itself modified. Timing of multiplication and summation processes is synchronized to the timing of the target display device and is performed during horizontal or vertical retrace line intervals. Additional summations of address values with the display parameters is performed by dot and line. It is, therefore, possible to achieve smooth image rotation without relying on high clock rate multiplication operations timed to the dot clock frequency by using a multiplication operation once every display frame or line, and a cumulative addition operation once every dot or display line. Multipliers can operate at a low clock rate, and time-shared use is possible, enabling the circuit to be constructed on a small scale and at low cost.
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Citations
28 Claims
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1. A display circuit for manipulating an image to be viewed on a display device, said display circuit comprising:
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a display memory containing pixel data defining a first image; an address counter for generating first addresses related to the order for reading the pixel data from the display memory for viewing the first image on the display device; parameter memory for storing rotation and scaling parameters for manipulating the first image; and a display operations controller for transforming the first addresses from the address counter into second addresses in accordance with the parameters from the parameter memory and for reading the pixel data in sequence from the display memory in accordance with the second addresses in synchronization with synchronization signals for the display device, the pixel data read from the display memory being outputted to the display device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
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28. A display circuit for manipulating an image to be viewed on a display device, said display circuit comprising:
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a display memory containing pixel data defining a first image; an address counter for generating first addresses related to the order for reading the pixel data from the display memory for viewing the first image on the display device in sequence in synchronization with synchronization signals for the display device; a parameter memory for storing rotation and scaling parameters for manipulating the first image; and a display controller for transforming the first addresses from the address counter into second addresses in accordance with the parameters from the parameter memory in synchronization with the synchronization signals and for reading the pixel data from the display memory in sequence in accordance with the second address in synchronization with the synchronization signals, the pixel data read from the display memory being outputted to the display device.
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Specification